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    • 8. 发明申请
    • Power supply controller
    • 电源控制器
    • US20070016313A1
    • 2007-01-18
    • US11261713
    • 2005-10-31
    • Yuuichi AbeKimiaki Taniguchi
    • Yuuichi AbeKimiaki Taniguchi
    • G05B11/01
    • G05B23/0237
    • A power supply controller with a function to identify whether or not a signal that was output is reliable and to perform the necessary processing on the input side when an unreliable signal was sent that might adversely affect the input side in communication systems. A controller 1 and a controlled device 21 are connected at both ends of a cable 17 (27) with connectors. The controller contains a first processing system 1, a second processing system 2, and a comparator 7. The first processing system and the second processing system 2 are for example equivalent to microcomputers, etc. The comparator 7 compares the outputs of these two processors and generates a match/mismatch signal according to whether the outputs are a match or not. When the two outputs are a match then the outputs of these processors are reliable. However if the outputs are a mismatch then it signifies there is an error in one of these processing systems. Either of these processors outputs a general output signal separate from the match/mismatch signal. The general output signal may be output from either the first processing system or the second processing system without passing through the comparator. The general output signal is converted to a contact signal. The match/mismatch signal functions to turn the monitor signal on the monitor signal line on and off. The actual connection for this (output signal line) is shown in the drawings. The monitor signal line forms a loop on the monitor signal line for the signal to move back and forth between the controller and the controlled device. The controlled device contains an internal open-identifier for sensing whether the control signal line is open or closed.
    • 一种电源控制器,具有识别输出信号是否可靠,并且当发送不可靠信号可能对通信系统中的输入侧产生不利影响时,在输入端执行必要的处理。 控制器1和受控设备21在具有连接器的电缆17(27)的两端连接。 控制器包含第一处理系统1,第二处理系统2和比较器7。 第一处理系统和第二处理系统2例如等同于微计算机等。比较器7比较这两个处理器的输出,并根据输出是否匹配产生匹配/失配信号。 当两个输出匹配时,这些处理器的输出是可靠的。 然而,如果输出是不匹配的,则表示这些处理系统之一存在错误。 这些处理器中的任何一个输出与匹配/失配信号分离的一般输出信号。 一般输出信号可以从第一处理系统或第二处理系统输出,而不通过比较器。 通用输出信号被转换为接点信号。 匹配/不匹配信号用于打开和关闭监视器信号线上的监视信号。 此(输出信号线)的实际连接如图所示。 监视器信号线在监视器信号线上形成一个环路,用于信号在控制器和受控设备之间来回移动。 受控设备包含用于检测控制信号线是打开还是关闭的内部开放标识符。
    • 10. 发明授权
    • Apparatus for calculating and prefetching a branch target address
    • 用于计算和预取分支目标地址的装置
    • US08578135B2
    • 2013-11-05
    • US13423145
    • 2012-03-16
    • Teppei HirotsuYuuichi AbeTakeshi KataokaYasuhiro Nakatsuka
    • Teppei HirotsuYuuichi AbeTakeshi KataokaYasuhiro Nakatsuka
    • G06F9/30G06F9/40G06F15/00
    • G06F9/30054G06F9/3804G06F9/382
    • A high-performance information processing technique permitting updating of an instruction buffer ready for effective prefetching to branch instructions and returning to the subroutine with a small volume of hardware is to be provided at low cost. It is an information processing apparatus equipped with a CPU, a memory, prefetch means and the like, wherein a prefetch address generator unit in the prefetch means decodes a branching series of instructions including at least one branched address calculating instruction and branching instruction to a branched address out of a current instruction buffer storing the series of instructions currently accessed by the CPU, and thereby looks ahead to the branching destination address. The information processing apparatus further comprises a RTS instruction buffer for storing a series of instructions of the return destinations of RTS instructions, and series of instructions stored in the current instruction buffer are saved into the RTS instruction buffer.
    • 能够以低成本提供允许更新准备好用于有效预取到分支指令并且以少量硬件返回到子程序的指令缓冲器的高性能信息处理技术。 它是配备有CPU,存储器,预取装置等的信息处理装置,其中预取装置中的预取地址发生器单元将包含至少一个分支地址计算指令和分支指令的分支指令序列解码为分支 从存储CPU当前访问的一系列指令的当前指令缓冲器中寻址,从而期待分支目的地址。 信息处理装置还包括RTS指令缓冲器,用于存储RTS指令的返回目的地的一系列指令,存储在当前指令缓冲器中的一系列指令被保存到RTS指令缓冲器中。