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1. 发明授权

US4462101A Maximum likelihood error correcting technique 失效
标题翻译：最大似然误差校正技术
公开(公告)号：US4462101A
公开(公告)日：1984-07-24
申请号：US355200
申请日：1982-03-05
申请人： Yutaka Yasuda , Yasuo Hirata , Akira Ogawa
发明人： Yutaka Yasuda , Yasuo Hirata , Akira Ogawa
IPC分类号： G06F11/10 , H03M13/23 , H04L1/00
CPC分类号： H04L1/0059 , H04L1/0054 , H04L1/0069
摘要： A maximum likelihood error correcting technique for a digital communication in which a transmit side provides coded data with some redundancy through a convolutional coding circuit, and a receive side corrects transmission errors automatically through a maximum likelihood error correcting circuit has been improved by deleting some symbols at a transmit side to increase a coding rate close to 1, and inserting dummy symbols at a receive side into each bit position where a symbol has been deleted at a transmit side. A likelihood value for that dummy symbol inserted at a receive side for the maximum likelihood decoding is a fixed predetermined value. Thus, both a coding circuit in a transmit side and a decoding circuit in a receiving circuit have only to handle original low rate code, while keeping a coding rate in a transmission line high. Then, the codec for high rate code obtained merely by adding the simple circuits to the simple codec for low rate code provides an excellent error correcting capability compared with other conventional error correcting techniques of the same coding rate.
摘要翻译：一种用于数字通信的最大似然纠错技术，其中发送侧通过卷积编码电路提供具有一定冗余度的编码数据，并且接收端通过最大似然误差校正电路自动校正传输错误已经通过删除一些符号在发送侧，以将编码率提高到接近1，并将接收侧的虚拟符号插入发送侧的符号被删除的每个比特位置。在接收侧插入用于最大似然解码的伪符号的似然值是固定的预定值。因此，发送侧的编码电路和接收电路中的解码电路都只能处理原始低速率码，同时保持传输线路中的编码率高。然后，与其他相同编码率的常规纠错技术相比，仅通过将简单电路添加到用于低速率代码的简单编解码器而获得的高速率代码的编解码器提供了出色的纠错能力。

2. 发明授权

US4578800A Synchronization circuit for a Viterbi decoder 失效
标题翻译：维特比解码器同步电路
公开(公告)号：US4578800A
公开(公告)日：1986-03-25
申请号：US511503
申请日：1983-07-06
申请人： Yutaka Yasuda , Yasuo Hirata , Shuji Murakami , Katsuhiro Nakamura , Yukitsuna Furuya
发明人： Yutaka Yasuda , Yasuo Hirata , Shuji Murakami , Katsuhiro Nakamura , Yukitsuna Furuya
IPC分类号： H03M13/33 , H04L7/00 , H04L7/02 , H04L7/04
CPC分类号： H03M13/33 , H04L7/0062
摘要： A Viterbi decoder synchronization circuit comprises a phase shifter for introducing a variable amount of delay time to a received bit stream of convolutional codes in response to a control signal applied thereto with respect to a word synchronization signal which is derived from the bit stream. A first detector detects maximum and minimum metric values of the Viterbi decoder. A second detector detects the difference between the detected maximum and minimum metric values for coupling to an integrator. The output of the integrator is applied to a third detector which detects when the integrator output reaches a value indicative of a word-in-sync or word-out-of-sync condition. A phase shift signal is generated in response to an output signal from the third detector and applied to the phase shifter as the control signal.
摘要翻译：维特比解码器同步电路包括一个移相器，用于响应于从比特流导出的字同步信号施加的控制信号，将可变量的延迟时间引入到所接收的卷积码比特流中。第一检测器检测维特比解码器的最大和最小度量值。第二检测器检测检测到的与积分器耦合的最大和最小度量值之间的差异。积分器的输出被施加到第三检测器，该第三检测器检测积分器输出何时达到指示同步字或字不同步条件的值。响应于来自第三检测器的输出信号产生相移信号，并将其作为控制信号施加到移相器。

3. 发明授权

US4527279A Synchronization circuit for a Viterbi decoder 失效
标题翻译：维特比解码器同步电路
公开(公告)号：US4527279A
公开(公告)日：1985-07-02
申请号：US511774
申请日：1983-07-06
申请人： Yutaka Yasuda , Yasuo Hirata , Shuji Murakami , Katsuhiro Nakamura , Yukitsuna Furuya
发明人： Yutaka Yasuda , Yasuo Hirata , Shuji Murakami , Katsuhiro Nakamura , Yukitsuna Furuya
IPC分类号： H03M13/33 , H04L7/04
CPC分类号： H03M13/33
摘要： A Viterbi decoder synchronization circuit comprises a circuit that derives a word synchronization signal from a received bit stream of convolutional codes. A first detector detects a maximum of metric values derived from the Viterbi decoder at different locations in time. A memory is provided for storing therein the address codes derived at different times and the maximum metric values detected by the first detector. A second detector is connected to the memory for detecting the presence of a path between the states addressed by the address codes stored in the memory. An integrator is connected to the second detector to integrate its output signal. To the integrator is connected a third detector which detects when the integrator output reaches a value indicative of one of word-in-sync and word-out-of-sync conditions of the Viterbi decoder. A phase shift signal is generated in response to an output signal from the third detector and applied to a phase shifter to introduce a delay time to the bit stream.
摘要翻译：维特比解码器同步电路包括从接收到的卷积码的比特流导出字同步信号的电路。第一检测器在不同的时间点检测从维特比解码器导出的度量值的最大值。提供存储器，用于在其中存储在不同时间导出的地址码和由第一检测器检测的最大度量值。第二检测器连接到存储器，用于检测由存储在存储器中的地址码寻址的状态之间的路径的存在。积分器连接到第二检测器以整合其输出信号。连接到积分器的第三检测器，其检测积分器输出何时达到表示维特比解码器的同步字和同步字的其中一个的值。响应于来自第三检测器的输出信号产生相移信号，并将其应用于移相器以向该比特流引入延迟时间。

4. 发明授权

US4456988A Satellite repeater 失效
标题翻译：卫星中继器
公开(公告)号：US4456988A
公开(公告)日：1984-06-26
申请号：US343181
申请日：1982-01-27
申请人： Yukio Nakagome , Akira Ogawa , Yasuo Hirata , Toshio Takahashi
发明人： Yukio Nakagome , Akira Ogawa , Yasuo Hirata , Toshio Takahashi
IPC分类号： H04B7/204 , H04B7/185 , H04J1/02
CPC分类号： H04B7/2046
摘要： A satellite repeater for a digital satellite communication system for use on board of satellites. Receivers are provided with respective antennas for receiving radio-frequency signals from a plurality of ground stations. A signal processing circuit switches signals received in synchronism with stable clock timings. Transmitters receive the switched outputs of the signal processing circuit to provide radio-frequency signals for transmission through respective antennas of the transmitters. Timing detectors receive the outputs of the receivers and detect the frame timings of the output signals of the receivers. Signal storage circuits are provided between respective outputs of the receivers and the signal processing circuit for storing the respective output signals of the receivers by respective amounts. Control circuitry connected to the timing detectors, the signal storage circuits and the signal processing circuit control the storage operations of the signal storage circuits so that each of the frame timings of the received signals and the switching timing of the signal processing circuit have a desired timing relationship.
摘要翻译：一种用于卫星上的数字卫星通信系统的卫星中继器。接收器设置有用于从多个地面站接收射频信号的相应天线。信号处理电路以稳定的时钟定时同步接收接收的信号。发射机接收信号处理电路的切换输出，以提供用于通过发射机的各个天线传输的射频信号。定时检测器接收接收机的输出并检测接收机的输出信号的帧定时。信号存储电路设置在接收机的各个输出端和信号处理电路之间，用于以相应的量存储接收机的相应输出信号。连接到定时检测器，信号存储电路和信号处理电路的控制电路控制信号存储电路的存储操作，使得接收信号的每个帧定时和信号处理电路的切换定时都具有期望的定时关系。

5. 发明授权

US4146893A System for compensating for cross polarization coupling 失效
标题翻译：用于补偿交叉极化耦合的系统
公开(公告)号：US4146893A
公开(公告)日：1979-03-27
申请号：US851810
申请日：1977-11-15
申请人： Kazunori Inagaki , Yasuo Hirata , Akira Ogawa
发明人： Kazunori Inagaki , Yasuo Hirata , Akira Ogawa
IPC分类号： H04J11/00 , H01Q21/24 , H01Q25/00 , H04B7/00 , H04B7/15
CPC分类号： H01Q25/001 , H01Q21/245 , H04B7/002
摘要： A system for compensating for cross polarization coupling in a dual-polarization satellite communication system, in which two polarized waves of the same frequency and orthogonal to each other are alternately transmitted as a pilot wave from an earth station at a predetermined period. The same polarized wave components of the two signals received by a communication satellite are sent back to the earth station, so that the sent back signal is received by the earth station. An amplitude ratio and a phase difference between the same polarized wave components of the two signals of the received pilot signal are detected. A communication signal wave to be transmitted from the earth station is formed as an elliptically polarized wave by the use of the detected information, thereby compensating for cross polarization coupling of the communication signal wave caused during propagation between the earth station and the communication satellite.

6. 发明授权

US4017684A System for determining burst sending timing in TDMA communication 失效
标题翻译：用于在TDMA通信中确定突发发送定时的系统
公开(公告)号：US4017684A
公开(公告)日：1977-04-12
申请号：US592717
申请日：1975-07-03
申请人： Hiroshi Kurihara , Akira Ogawa , Yasuo Hirata
发明人： Hiroshi Kurihara , Akira Ogawa , Yasuo Hirata
IPC分类号： H04J3/00 , H04B7/15 , H04B7/212 , H04J3/06 , H04L7/04 , H04L7/10
CPC分类号： H04B7/2125 , H04J3/0605 , H04L7/044 , H04L7/10
摘要： A system for determining burst sending timing in a time division multiple access communication system using a communication satellite, in which burst signals transmitted from a plurality of stations are arranged on the communication satellite in one frame at predetermined intervals. On the transmitting side connected to the communication satellite through a radio wave path, a first signal composed of a first signal state over one frame length defined by the sending frame timing is sent, and then second, third, fourth, . . . signals each composed of the first signal state and a second state different from the first signal state are sent. In this case, the position or length of the first signal state in one frame is altered by a certain amount. On the receiving side connected to the communication satellite through a radio wave path, the number of frames of the burst signals transmitted is counted during a duration from the detection of the first signal to the detection of the next first or second state at a predetermined time slot in a frame of the burst signals, and the sending timing of each station based on the sending frame timing is determined on the base of the counted number of frames and the certain amount.
摘要翻译：一种用于在使用通信卫星的时分多址通信系统中确定脉冲串发送定时的系统，其中从多个站发射的脉冲串信号以预定间隔一一帧地布置在通信卫星上。在通过无线电波路连接到通信卫星的发送侧，发送由由发送帧定时定义的一帧长度的第一信号状态组成的第一信号，然后是第二，第三，第四。。。发送各自由第一信号状态构成的信号和与第一信号状态不同的第二状态。在这种情况下，一帧中的第一信号状态的位置或长度被改变一定量。在通过无线电波路连接到通信卫星的接收侧，在从第一信号的检测到预定时间的下一个或第二状态的检测的持续时间期间，发送的突发信号的帧数被计数基于发送帧定时的每个站的发送定时，根据计数的帧数和一定量来确定突发信号的帧中的时隙。

7. 发明授权

US08400500B2 Endoscope with alternating irradiate light 有权
标题翻译：内镜与交替照射光
公开(公告)号：US08400500B2
公开(公告)日：2013-03-19
申请号：US11559197
申请日：2006-11-13
申请人： Yasuo Hirata
发明人： Yasuo Hirata
IPC分类号： A61B1/04 , A61B1/06
CPC分类号： A61B1/0607 , A61B1/0676 , A61B1/0684 , A61B1/128 , G02B23/2423 , G02B23/2461 , G02B23/2484
摘要： An endoscope that has an insertion portion that is inserted into an interior of an object and an image pickup device that is provided in the insertion portion, and that observes the interior of the object via the image pickup device, includes: a first LED unit that is provided in the insertion portion and has an LED chip that is used to irradiate light into the interior of the object; a second LED unit that is provided in the insertion portion and has an LED chip that is used to irradiate light into the interior of the object; and an alternating conduction control unit that conducts power alternatingly to the first LED unit and the second LED unit.
摘要翻译：具有插入到物体内部的插入部和设置在插入部中并且经由图像拾取装置观察物体内部的图像拾取装置的内窥镜包括：第一LED单元，其包括：设置在插入部分中，并且具有用于将光照射到物体内部的LED芯片; 第二LED单元，其设置在所述插入部中，并且具有用于将光照射到所述物体的内部的LED芯片; 以及交替导通控制单元，其交替地对第一LED单元和第二LED单元进行供电。

8. 发明授权

US07749160B2 Endoscope device 有权
标题翻译：内窥镜装置
公开(公告)号：US07749160B2
公开(公告)日：2010-07-06
申请号：US11616221
申请日：2006-12-26
申请人： Yasuo Hirata
发明人： Yasuo Hirata
IPC分类号： A61B1/06
CPC分类号： G02B23/2461 , A61B1/00096 , A61B1/00177 , A61B1/053 , A61B1/0607 , A61B1/0615 , A61B1/0676 , A61B1/0684 , G02B23/2423 , G02B23/2476 , G02B23/2492
摘要： An endoscope device includes an objective lens group that is provided at a distal end of an insertion portion that is inserted into a lumen of a subject and is used to observe or photograph the subject, and an illumination device that is provided at a distal end of the insertion portion and illuminates the subject using LED. The illumination device is provided with LED chips and an LED chip supporting block that supports these LED chips, and at least a portion of the objective lens group is mounted on the LED supporting block.
摘要翻译：一种内窥镜装置，其具备：物镜组，设置在插入到被检体内腔的插入部的前端，用于观察或拍摄被检体;以及照射装置，插入部分并使用LED照亮被摄体。照明装置设置有LED芯片和支撑这些LED芯片的LED芯片支撑块，并且物镜组的至少一部分安装在LED支撑块上。

9. 发明申请

US20080242927A1 COOLING APPARATUS FOR ENDOSCOPE AND ENDOSCOPE SYSTEM 有权
标题翻译：内窥镜和内窥镜系统的冷却装置
公开(公告)号：US20080242927A1
公开(公告)日：2008-10-02
申请号：US12048292
申请日：2008-03-14
申请人： Yasuo Hirata
发明人： Yasuo Hirata
IPC分类号： A61B1/12
CPC分类号： G02B23/2492
摘要： The endoscope cooling device is to cool an insertion portion having an observation portion at the distal end. The device is provided with an inner sheath into which the distal end portion of the insertion portion including the observation portion is inserted to form a first flow path of a cooling fluid between the outer circumferential face of the insertion portion and the inner circumferential face of the inner sheath, an outer sheath into which the inner sheath is inserted to form a second flow path of the cooling fluid between the outer circumferential face of the inner sheath and the inner circumferential face of the outer sheath, a regulating means for regulating the distal end portion in moving at least either through the inner sheath or the outer sheath, and a fluid supply means for supplying the cooling fluid to the first flow path and the second flow path.
摘要翻译：内窥镜冷却装置是在远端冷却具有观察部的插入部。该装置设置有内护套，插入部的前端部插入观察部的前端部，插入部的外周面与插入部的内周面之间形成冷却流体的第一流路内护套，外护套，内护套插入其中以在内护套的外周面和外护套的内周面之间形成冷却流体的第二流路;调节装置，用于调节远端至少通过内护套或外护套移动的部分，以及用于将冷却流体供应到第一流路和第二流路的流体供给装置。

10. 发明授权

US07000153B2 Computer apparatus and method of diagnosing the computer apparatus and replacing, repairing or adding hardware during non-stop operation of the computer apparatus 失效
标题翻译：计算机装置和方法，用于在计算机装置的不间断操作期间诊断计算机装置和更换，修理或添加硬件
公开(公告)号：US07000153B2
公开(公告)日：2006-02-14
申请号：US10160085
申请日：2002-06-04
申请人： Takashi Inagawa , Yasuo Hirata , Teiji Karasaki , Shinji Kimura
发明人： Takashi Inagawa , Yasuo Hirata , Teiji Karasaki , Shinji Kimura
IPC分类号： G06F11/00
CPC分类号： G06F11/26
摘要： A computer apparatus and a method of diagnosing are provided that increase reliability and make non-stop operation possible even at a hardware repair, replacement, or addition time. The computer apparatus, which comprises a main OS and a sub OS, may have a peripheral device or an I/O card repaired, replaced, or added with power on. The repaired, replaced, or added hardware component is disconnected from the main OS. With the main OS performing usual processing, the sub OS uses a test/maintenance program to check the operation of the repaired, replaced, or added hardware component and then passes the control of the hardware component to the main OS.
摘要翻译：提供一种计算机装置和诊断方法，即使在硬件维修，更换或添加时间也可提高可靠性并使不停机的操作成为可能。包括主OS和子OS的计算机装置可以具有修复，替换或添加电源的外围设备或I / O卡。已修复，更换或添加的硬件组件与主OS断开连接。在主OS执行通常处理的情况下，子OS使用测试/维护程序来检查已修复，替换或添加的硬件组件的操作，然后将硬件组件的控制传递到主OS。

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