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    • 1. 发明授权
    • Waveform analyzer and waveform analysis method
    • 波形分析仪和波形分析方法
    • US09339205B2
    • 2016-05-17
    • US13358776
    • 2012-01-26
    • Yutaka TamiyaHiroaki IwashitaHiroyuki Higuchi
    • Yutaka TamiyaHiroaki IwashitaHiroyuki Higuchi
    • A61B5/0452A61B5/0464G06K9/00G01R29/02
    • A61B5/04525A61B5/0464G01R29/02G06K9/00536
    • A waveform analyzer includes a converter which converts a logical function, where a pair of data including a time and a value at the time is variable, created according to data sets of a time and a value of a signal waveform at the time into a second function expressed by a binary decision diagram, an acquisition unit which obtains for each of characteristic points of a reference waveform a condition representative of constraints on a relationship between time information specified by the points and a value corresponding to the time information in the signal waveform according to a value of the reference waveform at the points and a specified tolerance given to a value of the reference waveform, and a searching unit which applies the condition for each of the points to the second function to obtain a time range which meets the entirety of the conditions.
    • 波形分析器包括转换器,其转换逻辑功能,其中包括时间和时间上的值的一对数据是可变的,根据时间的数据集和当时的信号波形的值创建为第二 函数由二进制判定图表示,获取单元,其针对参考波形的每个特征点获得表示由点指定的时间信息与对应于信号波形中的时间信息的值之间的关系的条件的条件, 相对于参考波形的参考波形的值和对参考波形的值给出的规定的公差,以及搜索单元,其将每个点的条件应用于第二函数,以获得满足整个 条件。
    • 2. 发明申请
    • WAVEFORM ANALYZER AND WAVEFORM ANALYSIS METHOD
    • 波形分析仪和波形分析方法
    • US20120239328A1
    • 2012-09-20
    • US13358776
    • 2012-01-26
    • Yutaka TAMIYAHiroaki IwashitaHiroyuki Higuchi
    • Yutaka TAMIYAHiroaki IwashitaHiroyuki Higuchi
    • G06F19/00G01R29/00
    • A61B5/04525A61B5/0464G01R29/02G06K9/00536
    • A waveform analyzer includes a converter which converts a logical function, where a pair of data including a time and a value at the time is variable, created according to data sets of a time and a value of a signal waveform at the time into a second function expressed by a binary decision diagram, an acquisition unit which obtains for each of characteristic points of a reference waveform a condition representative of constraints on a relationship between time information specified by the points and a value corresponding to the time information in the signal waveform according to a value of the reference waveform at the points and a specified tolerance given to a value of the reference waveform, and a searching unit which applies the condition for each of the points to the second function to obtain a time range which meets the entirety of the conditions.
    • 波形分析器包括转换器,其转换逻辑功能,其中包括时间和时间上的值的一对数据是可变的,根据时间的数据集和当时的信号波形的值创建为第二 函数由二进制判定图表示,获取单元,其针对参考波形的每个特征点获得表示由点指定的时间信息与对应于信号波形中的时间信息的值之间的关系的条件的条件, 相对于参考波形的参考波形的值和对参考波形的值给出的规定的公差,以及搜索单元,其将每个点的条件应用于第二函数,以获得满足整个 条件。
    • 5. 发明申请
    • Method and device for supporting verification, and computer product
    • 支持验证的方法和设备,以及计算机产品
    • US20070168894A1
    • 2007-07-19
    • US11520940
    • 2006-09-14
    • Hiroaki Iwashita
    • Hiroaki Iwashita
    • G06F17/50
    • G06F17/5022G01R31/31703G01R31/318342G01R31/318357
    • In a verification support device, a logical expression expressing an operation of a pattern generator can be acquired. The pattern generator includes a basic pattern generator, priority pattern generators, priority pattern selection conditions, and selector circuits. The selector circuits connect the basic pattern generator, the priority pattern generators, and the priority pattern selection conditions. Output of the basic pattern generator and outputs of the priority pattern generators are respectively connected to a signal input of a corresponding selector circuit. Outputs of the priority pattern selection conditions are connected to an ON/OFF control input of each selector circuit. An n-th selector circuit, among all selector circuits, is connected to an input terminal of a verification subject.
    • 在验证支持设备中,可以获取表达模式生成器的操作的逻辑表达式。 模式发生器包括基本模式生成器,优先模式生成器,优先模式选择条件和选择器电路。 选择器电路连接基本模式发生器,优先模式发生器和优先模式选择条件。 基本模式发生器的输出和优先模式发生器的输出分别连接到相应选择器电路的信号输入端。 优先模式选择条件的输出连接到每个选择器电路的ON / OFF控制输入。 所有选择电路中的第n选择器电路连接到验证对象的输入端。
    • 8. 发明授权
    • Clock domain crossing verification support
    • 时钟域交叉验证支持
    • US08407636B2
    • 2013-03-26
    • US12962785
    • 2010-12-08
    • Hiroaki Iwashita
    • Hiroaki Iwashita
    • G06F17/50G06F9/455
    • G06F17/5022G06F2217/62
    • A computer-readable, non-transitory medium stores therein a verification support program that causes a computer to execute a procedure. The procedure includes first detecting a state change in a circuit and occurring when input data is given to the circuit. The procedure also includes second detecting a state change in the circuit and occurring when the input data partially altered is given to the circuit. The procedure further includes determining whether a difference exists between a series of state changes detected at the first detecting and a series of state changes detected at the second detecting. The procedure also includes outputting a determination result obtained at the determining.
    • 计算机可读的非暂时性介质中存储有使计算机执行过程的验证支持程序。 该过程包括首先检测电路中的状态变化并且当输入数据被提供给电路时发生。 该过程还包括第二检测电路中的状态变化,并且当将输入数据部分地改变为电路时发生。 该过程还包括确定在第一检测期间检测到的一系列状态变化与在第二检测时检测到的一系列状态变化之间是否存在差异。 该过程还包括输出在确定时获得的确定结果。
    • 10. 发明申请
    • VERIFICATION SUPPORT APPARATUS, VERIFYING APPARATUS, COMPUTER PRODUCT, VERIFICATION SUPPORT METHOD, AND VERIFYING METHOD
    • 验证支持设备,验证设备,计算机产品,验证支持方法和验证方法
    • US20120210282A1
    • 2012-08-16
    • US13298354
    • 2011-11-17
    • Hiroaki Iwashita
    • Hiroaki Iwashita
    • G06F9/455G06F17/50
    • G06F17/5022G06F2217/62
    • A verification support apparatus includes a detecting unit that detects an inconsistency between a simulation result at an observation point in a circuit-under-test and an expected value; a setting unit that sets a portion of output values to logic values different from those of the simulation result when the detecting unit detects the inconsistency, wherein the output values are random values output from elements that receive a signal in a second clock domain that receives the signal from a first clock domain asynchronously; a comparing unit that compares the expected value and a simulation result at the observation point after the setting by the setting unit; and an identifying unit that identifies whether the portion of the output values are a cause of the inconsistency, based on a result of comparison by the comparing unit.
    • 验证支持装置包括:检测单元,其检测被测电路中的观测点的模拟结果与预期值之间的不一致; 设置单元,当检测单元检测到不一致时,将输出值的一部分设置为与模拟结果不同的逻辑值,其中,输出值是从接收第二时钟域中的信号的单元输出的随机值 来自第一时钟域的信号异步; 比较单元,其将设定单元设定后的观察点的期望值和模拟结果进行比较; 以及识别单元,其基于比较单元的比较结果来识别输出值的部分是否是不一致的原因。