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1. 发明授权

US06658497B1 System for recognizing of a device connection state by reading structure information data which produced by pull-up resistor and pull-down resistor 失效
标题翻译：通过读取由上拉电阻和下拉电阻产生的结构信息数据来识别器件连接状态的系统
公开(公告)号：US06658497B1
公开(公告)日：2003-12-02
申请号：US09376482
申请日：1999-08-18
申请人： Yusuke Kawasaki , Shigeru Hashimoto , Koken Yamamoto
发明人： Yusuke Kawasaki , Shigeru Hashimoto , Koken Yamamoto
IPC分类号： G06F300
CPC分类号： G06F13/4068
摘要： The present invention relates to a device connection state recognizing method capable of recognizing a connection state of devices without addition of signal lines dedicated to detection. Thus, in the method according to this invention, a portion of or all of a plurality of data signal lines are connected through pull-up resistors to a high electric potential or connected through pull-down resistors to a low electric potential in accordance with the connection state of the devices, and a processing unit reads, as structure information data, a high electric potential state/low electric potential state generated by the pull-up resistor/pull-down resistor in the portion of or all the plurality of data signal lines to recognize the connection state of the devices on the basis of the read structure information data. This invention is applicable to a various types of processing units which are to be connected through a common data bus to a plurality of devices.
摘要翻译：本发明涉及能够识别设备的连接状态而不添加专用于检测的信号线的设备连接状态识别方法。因此，在根据本发明的方法中，多个数据信号线的一部分或全部通过上拉电阻器连接到高电位或通过下拉电阻器连接到低电位，根据设备的连接状态，并且处理单元读取作为结构信息数据的多个数据信号的部分或全部由上拉电阻器/下拉电阻器产生的高电位状态/低电位状态根据读结构信息数据识别设备的连接状态。本发明可应用于通过公共数据总线连接到多个设备的各种类型的处理单元。

2. 发明授权

US06968995B1 Integrated circuit for protocol control 失效
标题翻译：用于协议控制的集成电路
公开(公告)号：US06968995B1
公开(公告)日：2005-11-29
申请号：US09376308
申请日：1999-08-18
申请人： Koken Yamamoto , Shigeru Hashimoto , Ryoichi Yanagi , Yusuke Kawasaki
发明人： Koken Yamamoto , Shigeru Hashimoto , Ryoichi Yanagi , Yusuke Kawasaki
IPC分类号： G07D13/00 , G06F15/78 , G06F19/00 , G06K17/00 , G06Q20/00 , G06Q20/06 , G06Q20/20 , G06Q20/30 , G06Q40/00 , G06Q40/02 , G07F7/08 , G07F7/10 , G07F19/00 , G06F17/60
CPC分类号： G07F7/1008 , G06Q20/341 , G06Q20/346 , G06Q20/3552 , G06Q20/3578 , G06Q20/363 , G06Q20/40975 , G06Q40/00 , G07F7/0866
摘要： A protocol control integrated circuit configured by integrating, on one chip, hardware and control programs necessary for conducting data interchange through communications with portable type mediums, and used in common among various types of apparatus. Thus, the integrated circuit is constructed by integrating, on one chip, a storage section for storing a control program prepared for protocols for a plurality of digital money different in mode from each other, a processing section for controlling the handling of the plurality of digital money, different in mode, by running the control program stored in the storage section, and an interface circuit connected to an external circuit including at least one of an external processing section and an external storage section for fulfilling an interface function between the external circuit and the processing section. Further this invention is applicable to various types of transaction apparatus capable of handling, for example, digital money and credit transactions.
摘要翻译：一种协议控制集成电路，其通过在一个芯片上集成通过与便携式介质通信进行数据交换所需的硬件和控制程序，并且在各种类型的设备中共同使用。因此，集成电路是通过在一个芯片上集成存储部分，用于存储为彼此不同模式的多个数字货币的协议而准备的控制程序，用于控制多个数字的处理的处理部分钱，不同的模式，通过运行存储在存储部分中的控制程序，以及连接到外部电路的接口电路，该外部电路包括外部处理部分和外部存储部分中的至少一个，用于实现外部电路和处理部分。此外，本发明可应用于能够处理例如数字货币和信用交易的各种交易装置。

3. 发明授权

US06519650B1 System and method for controlling data transfer between portable medias and a processor to minimize communication hardware requirements 失效
标题翻译：用于控制便携式媒体和处理器之间的数据传输的系统和方法，以最小化通信硬件要求
公开(公告)号：US06519650B1
公开(公告)日：2003-02-11
申请号：US09376467
申请日：1999-08-18
申请人： Yusuke Kawasaki , Shigeru Hashimoto , Koken Yamamoto
发明人： Yusuke Kawasaki , Shigeru Hashimoto , Koken Yamamoto
IPC分类号： G06F15173
CPC分类号： G07F7/1008 , G06Q20/341 , G07F7/084
摘要： The present invention relates to a method and system capable of gaining access (data transfer) to portable type mediums whose number is larger than the number of ports on a processing unit side. Thus, in this invention, by using a demultiplexer, to one or more portable type medium ports provided in a processing unit there are connected a plurality of portable type mediums whose number is larger than the number of the ports. The demultiplexer selectively switches the ports and, of the plurality of portable type mediums, the mediums to be accessed by the processing unit for establishing the connections therebetween. This invention is applicable to data transfer between a plurality of portable type mediums such as IC cards capable of storing digital money and a processing unit having an ability to gain access to these portable type mediums.
摘要翻译：本发明涉及一种方法和系统，其能够获得对数量大于处理单元侧的端口数的便携式媒体的访问（数据传送）。因此，在本发明中，通过使用解复用器，对于设置在处理单元中的一个或多个便携式介质端口，连接多个数量大于端口数量的便携式介质。多路复用器选择性地切换多个便携式介质中的端口，以便由处理单元访问的介质以建立它们之间的连接。本发明可应用于能够存储数字货币的多个便携式媒体之类的数据传输和具有访问这些便携式媒体的能力的处理单元。

4. 发明授权

US07657758B2 Processing apparatus and integrated circuit to prevent illicit access and reverse engineering 有权
标题翻译：处理装置和集成电路，以防止非法访问和逆向工程
公开(公告)号：US07657758B2
公开(公告)日：2010-02-02
申请号：US09739839
申请日：2000-12-20
申请人： Yusuke Kawasaki , Hiroshi Sakurai , Shigeru Hashimoto , Koken Yamamoto
发明人： Yusuke Kawasaki , Hiroshi Sakurai , Shigeru Hashimoto , Koken Yamamoto
IPC分类号： G06F12/14 , G06F1/06 , G06F21/22 , H04L9/16
CPC分类号： G06F21/75 , G06F12/1408
摘要： A processing apparatus including an internal circuit having a CPU and internal devices and an external circuit including external devices provided externally of the internal circuit, and the like, and is aimed to prevent illicit access and reverse engineering. The internal circuit including a CPU, internal devices and a bus line connecting the CPU to the internal devices and extending externally, and the external circuit including external devices provided externally of an externally extending portion of the bus line. The internal circuit further including a ciphering section 120 provided at an entrance to an external side and ciphering addresses and data on the bus line by ciphering patterns according to a plurality of regions divided from an address space allotted to the entire external devices.
摘要翻译：一种处理装置，包括具有CPU和内部装置的内部电路和包括在内部电路外部提供的外部装置的外部电路等，并且旨在防止非法访问和逆向工程。内部电路包括CPU，内部设备和将CPU连接到内部设备并从外部延伸的总线，外部电路包括外部设备，其外部设置在总线的外部延伸部分上。内部电路还包括设置在外部入口处的加密部分120，并且根据从分配给整个外部设备的地址空间划分的多个区域通过加密模式来加密总线上的地址和数据。

5. 发明授权

US07039779B2 Access monitor and access monitoring method for monitoring access between programs 失效
标题翻译：访问监控和访问监控方法，用于监控程序之间的访问
公开(公告)号：US07039779B2
公开(公告)日：2006-05-02
申请号：US09739885
申请日：2000-12-20
申请人： Yusuke Kawasaki , Shigeru Hashimoto , Koken Yamamoto , Tomomi Shiobara , Ryoichi Yanagi
发明人： Yusuke Kawasaki , Shigeru Hashimoto , Koken Yamamoto , Tomomi Shiobara , Ryoichi Yanagi
IPC分类号： G06F12/14
CPC分类号： G06F12/1483 , G06F21/554 , G06F21/78
摘要： An access violation of the program is monitored by the access monitor which is a hardware. The access monitor acquires a signal input from the CPU to a memory. The access monitor includes an access permission table as information of the memory region to be permitted to each program, and detects the access violation of the signal from the CPU by referring thereto. In this manner, the unjust access is monitored by the hardware, thereby preventing the unjust access by rewriting in software.
摘要翻译：程序的访问冲突由作为硬件的访问监视器监视。访问监视器获取从CPU向存储器输入的信号。访问监视器包括作为要被允许到每个程序的存储器区域的信息的访问许可表，并且通过参考来检测来自CPU的信号的访问冲突。以这种方式，硬件监视不正当的访问，从而通过软件重写来防止不正当的访问。

6. 发明授权

US06993654B2 Secure encryption processor with tamper protection 失效
标题翻译：安全加密处理器具有防篡改
公开(公告)号：US06993654B2
公开(公告)日：2006-01-31
申请号：US09733912
申请日：2000-12-12
申请人： Yuji Seki , Yusuke Kawasaki , Shigeru Hashimoto , Ryoichi Yanagi
发明人： Yuji Seki , Yusuke Kawasaki , Shigeru Hashimoto , Ryoichi Yanagi
IPC分类号： H04L9/00 , H04L9/32 , G06F11/30 , G06F12/14
CPC分类号： G07F7/1008 , G06F21/6209 , G06F21/72 , G06F21/85 , G06F2221/2153 , G06Q20/341 , G06Q20/40975 , G07F7/082 , G07F7/1016 , H04L63/0428
摘要： An encryption processor for encrypting and decrypting data that ensures data security by preventing illegal deciphering or leakage of the data. The encryption processor includes a CPU for running a program, a ROM for storing the program run by the CPU, a RAM used as a work area while the CPU is running the program, an I/O section for sending/receiving data to/from an external device, and an encryption section for decrypting encrypted data and encrypting plain text data.
摘要翻译：一种用于加密和解密数据的加密处理器，通过防止数据的非法解密或泄露来确保数据安全。加密处理器包括用于运行程序的CPU，用于存储由CPU运行的程序的ROM，在CPU运行程序时用作工作区的RAM;用于向/从...发送/接收数据的I / O部分外部设备和用于对加密数据进行解密和加密明文数据的加密部分。

7. 发明授权

US07080258B2 IC, IC-mounted electronic device, debugging method and IC debugger 失效
标题翻译： IC，IC安装电子设备，调试方法和IC调试器
公开(公告)号：US07080258B2
公开(公告)日：2006-07-18
申请号：US09784151
申请日：2001-02-16
申请人： Yusuke Kawasaki , Shigeru Hashimoto
发明人： Yusuke Kawasaki , Shigeru Hashimoto
IPC分类号： G06F11/30 , G06F12/14 , G06F9/44 , H04L9/32
CPC分类号： G06F11/3656 , G01R31/31719 , G06F21/75
摘要： Authentication circuits are provided between a debug I/F circuit and a debug terminal. The authentication circuit transmits a transmission key externally at the time of activation, and authenticates based on a reception signal and the transmission key, and enables access to the debug I/F. Thus, it is possible to prevent a spurious access from the debug I/F by a third person by the authentication circuit.
摘要翻译：在调试I / F电路和调试终端之间提供认证电路。认证电路在激活时从外部发送传输密钥，并且基于接收信号和传输密钥进行认证，并且能够访问调试I / F。因此，可以防止认证电路由第三人员从调试I / F进行的伪访问。

8. 发明授权

US06952822B2 Program installation method, program installation system, program executing apparatus, and storage medium 有权
标题翻译：程序安装方法，程序安装系统，程序执行装置和存储介质
公开(公告)号：US06952822B2
公开(公告)日：2005-10-04
申请号：US09774629
申请日：2001-02-01
申请人： Tomomi Shiobara , Yusuke Kawasaki , Shigeru Hashimoto
发明人： Tomomi Shiobara , Yusuke Kawasaki , Shigeru Hashimoto
IPC分类号： G06F12/14 , G06F9/445 , G06F21/00 , G06F21/24 , G06F9/44
CPC分类号： G07F19/206 , G06F8/61 , G06F21/51
摘要： The installation method makes possible the installation of new programs, while maintaining security, in a system LSI device. The installation method comprises a step for receiving the signature data 7 of a program 6, a step for checking for interference with other already installed programs on the basis of said signature data 7, and a step for authorizing the installation of programs with which there is no interference. A declaration of signature data is elicited from a program being installed; a check for interference among programs is performed based on this, authentication is performed, and the installation of interfering programs is prevented or the installation of programs with which there is no interference is executed. It therefore becomes possible to install new programs while protecting high-security programs.
摘要翻译：安装方法可以在系统LSI设备中安装新程序，同时保持安全性。该安装方法包括：接收程序6的签名数据7的步骤，基于所述签名数据7检查与其他已经安装的程序的干扰的步骤;以及授权安装程序的步骤无干扰从正在安装的程序中引出签名数据的声明; 基于此执行对程序之间的干扰的检查，执行认证，并且防止安装干扰程序或执行不具有干扰的程序的安装。因此，可以在保护高安全性程序的同时安装新程序。

9. 发明授权

US06549993B2 Contents check method, contents renewal method and processing apparatus 失效
公开(公告)号：US06549993B2
公开(公告)日：2003-04-15
申请号：US09731800
申请日：2000-12-08
申请人： Yusuke Kawasaki , Hiroshi Sakurai , Shigeru Hashimoto
发明人： Yusuke Kawasaki , Hiroshi Sakurai , Shigeru Hashimoto
IPC分类号： G06F1314
CPC分类号： G06F21/51 , G06F11/1004 , G06F21/64
摘要： In a system having an internal memory storing internal contents wherein an external memory for storing external contents is detachably mounted on said processing apparatus, for performing a processing according to the internal contents stored in said internal memory and the external contents stored in said external memory, a contents check method decides validity of the external contents stored in said external memory. The external contents stored in said external memory involve original check result information representative of a check result associated with validity of the external contents and original check result position information representative of a storage position of the original check result information. The external contents stored in said external memory is checked in accordance with a predetermined check algorithm to obtain a check result. The check result obtained is compared with a check result represented by the original check result information stored in a storage position indicated by the original check result position information to decide validity of the external contents stored in said external memory.

10. 发明授权

US06608995B1 Detection circuit for proximity IC card device 失效
标题翻译：接近IC卡设备检测电路
公开(公告)号：US06608995B1
公开(公告)日：2003-08-19
申请号：US09503356
申请日：2000-02-14
申请人： Yusuke Kawasaki , Yoshiyasu Sugimura , Shigeru Hashimoto
发明人： Yusuke Kawasaki , Yoshiyasu Sugimura , Shigeru Hashimoto
IPC分类号： H04B500
CPC分类号： H04B5/0012 , G06K7/0008
摘要： The present invention relates to a proximity IC card (PICC). More particularly, the present invention relates to and provides a detection circuit of a simple structure, which is easy to set up in a PICC and a proximity coupling device (PCD) for transmitting data to and receiving data from the PICC. This detection circuit is operative to detect a subcarrier signal sent from a PICC and superposed onto a carrier signal received through an antenna. Further, this detection circuit comprises a bias circuit for applying predetermined DC potential to a signal received from the antenna, a rectifier circuit for extracting a subcarrier signal superposed onto the carrier signal by rectifying a signal received from the antenna at a bias point, and an amplifier circuit for amplifying the subcarrier signal extracted at the bias point.
摘要翻译：本发明涉及一种接近IC卡（PICC）。更具体地说，本发明涉及并提供一种简单结构的检测电路，其易于在PICC和邻近耦合器件（PCD）中建立，用于向PICC发送数据并从PICC接收数据。该检测电路用于检测从PICC发送并叠加到通过天线接收的载波信号上的副载波信号。此外，该检测电路包括用于对从天线接收的信号施加预定的DC电位的偏置电路，整流电路，用于通过在偏置点整流从天线接收的信号来提取叠加在载波信号上的副载波信号，以及放大器电路，用于放大在偏置点处提取的副载波信号。

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