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1. 发明授权

US08434047B1 Multi-level clock gating circuitry transformation 有权
标题翻译：多级时钟门控电路转换
公开(公告)号：US08434047B1
公开(公告)日：2013-04-30
申请号：US13013024
申请日：2011-01-25
申请人： Yunjian (William) Jiang , Arvind Srinivasan , Joy Banerjee , Yinghua Li , Partha Das , Samit Chaudhuri
发明人： Yunjian (William) Jiang , Arvind Srinivasan , Joy Banerjee , Yinghua Li , Partha Das , Samit Chaudhuri
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5031 , G06F2217/08
摘要： A method of optimizing clock-gated circuitry in an integrated circuit (IC) design is provided. A plurality of signals which feed into enable inputs of a plurality of clock gates is determined, where the clock gates gate a plurality of sequential elements in the IC design. Combinational logic which is shared among the plurality of signals is identified. The clock-gated circuitry is transformed into multiple levels of clock-gating circuitry based on the shared combinational logic.
摘要翻译：提供了一种在集成电路（IC）设计中优化时钟选通电路的方法。确定馈送到多个时钟门的使能输入的多个信号，其中时钟门选通IC设计中的多个顺序元件。识别在多个信号之间共享的组合逻辑。时钟门控电路基于共享组合逻辑转换为多级时钟门控电路。

2. 发明申请

US20080301594A1 Method For Optimized Automatic Clock Gating 有权
标题翻译：优化自动时钟门控方法
公开(公告)号：US20080301594A1
公开(公告)日：2008-12-04
申请号：US12128574
申请日：2008-05-28
申请人： Yunjian (William) Jiang , Arvind Srinivasan , Joy Banerjee , Yinghua Li , Partha Das , Samit Chaudhuri
发明人： Yunjian (William) Jiang , Arvind Srinivasan , Joy Banerjee , Yinghua Li , Partha Das , Samit Chaudhuri
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5031 , G06F2217/08
摘要： A method of optimizing clock-gated circuitry in an integrated circuit (IC) design is provided. A plurality of signals which feed into enable inputs of a plurality of clock gates is determined, where the clock gates gate a plurality of sequential elements in the IC design. Combinational logic which is shared among the plurality of signals is identified. The clock-gated circuitry is transformed into multiple levels of clock-gating circuitry based on the shared combinational logic.
摘要翻译：提供了一种在集成电路（IC）设计中优化时钟选通电路的方法。确定馈送到多个时钟门的使能输入的多个信号，其中时钟门选通IC设计中的多个顺序元件。识别在多个信号之间共享的组合逻辑。时钟门控电路基于共享组合逻辑转换为多级时钟门控电路。

3. 发明申请

US20080301593A1 Method For Automatic Clock Gating To Save Power 有权
标题翻译：自动时钟门控的方法来节省电量
公开(公告)号：US20080301593A1
公开(公告)日：2008-12-04
申请号：US12128554
申请日：2008-05-28
申请人： Yunjian (William) Jiang , Arvind Srinivasan , Joy Banerjee , Yinghua Li , Partha Das , Samit Chaudhuri
发明人： Yunjian (William) Jiang , Arvind Srinivasan , Joy Banerjee , Yinghua Li , Partha Das , Samit Chaudhuri
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5031 , G06F2217/08
摘要： A power optimization method of deriving gated circuitry in a synthesized netlist of an integrated circuit (IC) design is provided. A block in the synthesized netlist is identified as an idle candidate block. Sub-blocks on the chip are clustered into a cluster. For the cluster, a clock gating structure optimized for power savings is determined, based on the idle candidate block. One or more inflexible clock gates are inserted in the netlist according to the clock gate structure.
摘要翻译：提供了一种在集成电路（IC）设计的综合网表中导出门控电路的功率优化方法。合成网表中的块被标识为空闲候选块。芯片上的子块被聚集成一个集群。对于集群，基于空闲候选块确定针对功率节省优化的时钟门控结构。根据时钟门结构，在网表中插入一个或多个不灵活的时钟门。

4. 发明授权

US07930673B2 Method for automatic clock gating to save power 有权
标题翻译：自动时钟门控功能的节省方法
公开(公告)号：US07930673B2
公开(公告)日：2011-04-19
申请号：US12128554
申请日：2008-05-28
申请人： Yunjian (William) Jiang , Arvind Srinivasan , Joy Banerjee , Yinghua Li , Partha Das , Samit Chaudhuri
发明人： Yunjian (William) Jiang , Arvind Srinivasan , Joy Banerjee , Yinghua Li , Partha Das , Samit Chaudhuri
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5031 , G06F2217/08
摘要： A power optimization method of deriving gated circuitry in a synthesized netlist of an integrated circuit (IC) design is provided. A block in the synthesized netlist is identified as an idle candidate block. Sub-blocks on the chip are clustered into a cluster. For the cluster, a clock gating structure optimized for power savings is determined, based on the idle candidate block. One or more inflexible clock gates are inserted in the netlist according to the clock gate structure.
摘要翻译：提供了一种在集成电路（IC）设计的综合网表中导出门控电路的功率优化方法。合成网表中的块被标识为空闲候选块。芯片上的子块被聚集成一个集群。对于集群，基于空闲候选块确定针对功率节省优化的时钟门控结构。根据时钟门结构，在网表中插入一个或多个不灵活的时钟门。

5. 发明授权

US07882461B2 Method for optimized automatic clock gating 有权
标题翻译：优化自动时钟门控的方法
公开(公告)号：US07882461B2
公开(公告)日：2011-02-01
申请号：US12128574
申请日：2008-05-28
申请人： Yunjian (William) Jiang , Arvind Srinivasan , Joy Banerjee , Yinghua Li , Partha Das , Samit Chaudhuri
发明人： Yunjian (William) Jiang , Arvind Srinivasan , Joy Banerjee , Yinghua Li , Partha Das , Samit Chaudhuri
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5031 , G06F2217/08
摘要： A method of optimizing clock-gated circuitry in an integrated circuit (IC) design is provided. A plurality of signals which feed into enable inputs of a plurality of clock gates is determined, where the clock gates gate a plurality of sequential elements in the IC design. Combinational logic which is shared among the plurality of signals is identified. The clock-gated circuitry is transformed into multiple levels of clock-gating circuitry based on the shared combinational logic.
摘要翻译：提供了一种在集成电路（IC）设计中优化时钟选通电路的方法。确定馈送到多个时钟门的使能输入的多个信号，其中时钟门选通IC设计中的多个顺序元件。识别在多个信号之间共享的组合逻辑。时钟门控电路基于共享组合逻辑转换为多级时钟门控电路。

6. 发明申请

US20160267387A1 METHODS AND SYSTEMS FOR PREDICTING ERRONEOUS BEHAVIOR OF AN ENERGY ASSET USING FOURIER BASED CLUSTERING TECHNIQUE 审中-公开
标题翻译：使用基于FOURIER的聚类技术预测能源资产的错误行为的方法和系统
公开(公告)号：US20160267387A1
公开(公告)日：2016-09-15
申请号：US14746535
申请日：2015-06-22
申请人： Baburaj Kaimalilputhenpura PRABHA , Joy Banerjee
发明人： Baburaj Kaimalilputhenpura PRABHA , Joy Banerjee
IPC分类号： G06N5/04
CPC分类号： G06N99/005 , G06K9/00523 , H02J3/00 , H02J2003/007
摘要： This disclosure relates generally to predicting health of an energy asset, and more particularly to methods and systems for predicting erroneous behavior of an energy asset using fourier based clustering technique. In one embodiment, a method for determining predicting erroneous behavior of an energy asset is disclosed. The method includes creating one or more energy signatures by performing frequency domain analysis on historical energy data and subsequent clustering of the energy signatures. Further, live energy data is filtered to generate filtered outputs wherein each of the filtered outputs is mapped to a respective cluster. The outlier cluster is identified to predict the erroneous behavior of the energy asset
摘要翻译：本公开一般涉及预测能量资产的健康状况，更具体地涉及使用基于傅立叶的聚类技术来预测能量资产的错误行为的方法和系统。在一个实施例中，公开了一种用于确定预测能量资产的错误行为的方法。该方法包括通过对能量特征的历史能量数据和随后的聚类执行频域分析来创建一个或多个能量签名。此外，对活能数据进行滤波以产生滤波的输出，其中每个滤波的输出被映射到相应的簇。确定异常群集以预测能源资产的错误行为

7. 发明授权

US07076748B2 Identification and implementation of clock gating in the design of integrated circuits 有权
标题翻译：时钟门控在集成电路设计中的识别与实现
公开(公告)号：US07076748B2
公开(公告)日：2006-07-11
申请号：US10631755
申请日：2003-08-01
申请人： Bhanu Kapoor , Sanjay Churiwala , Joy Banerjee
发明人： Bhanu Kapoor , Sanjay Churiwala , Joy Banerjee
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/62
摘要： Identification and implementation of clock gating in the design of an integrated circuit (IC) is performed with automated assistance. Electrical power consumption is reduced by clock gating. The automated assistance identifies registers that are candidates for clock gating, and highlights, in the IC design, registers associated with a gated clock domain and the logic blocks driven by these registers.
摘要翻译：集成电路（IC）设计中时钟选通的识别和实现是通过自动化辅助进行的。通过时钟门控降低功耗。自动化帮助识别作为时钟门控的候选者的寄存器，并且在IC设计中突出显示与门控时钟域相关联的寄存器以及由这些寄存器驱动的逻辑块。

8. 发明申请

US20080123138A1 Image Fit To Media Area Method 审中-公开
标题翻译：图像适合媒体区域方法
公开(公告)号：US20080123138A1
公开(公告)日：2008-05-29
申请号：US11564359
申请日：2006-11-29
申请人： Joy Banerjee , Terrance Lee Druggan , William Roger Steen
发明人： Joy Banerjee , Terrance Lee Druggan , William Roger Steen
IPC分类号： G06K15/00
CPC分类号： H04N1/387 , H04N1/00132 , H04N1/00167 , H04N1/00188
摘要： Images may be arranged in a minimal number of media areas through a recurring process of positioning an image within a white space of the media area and subdividing the white space into an image space in which the image is positioned, a second white space, and a third white space. The second white space occupies a region of the first white space not occupied by the first image along a first direction while the third white space occupies a region of the first white space not occupied by the image along a second direction. Then, subsequent images may be positioned within the unoccupied white spaces if the images spatially fit in one of an original or rotated orientation. As images are placed into unoccupied white spaces, the white spaces may be further subdivided.
摘要翻译：图像可以通过将图像定位在介质区域的白色空间内的循环过程而被布置在最少数量的介质区域中，并且将白色空间细分成图像定位的图像空间，第二空白区域和第三个空白。第二白色空间沿着第一方向占据未被第一图像占据的第一白色空间的区域，而第三白色空间占据第二空间未被图像占据的第一白色空间的区域。然后，如果图像以原始或旋转方向空间拟合，则后续图像可以被定位在未占用的空白空间内。当图像被放置到空闲空白处时，可以进一步细分空白区域。

9. 发明申请

US20050028118A1 Identification and implementation of clock gating in the design of integrated circuits 有权
标题翻译：时钟门控在集成电路设计中的识别与实现
公开(公告)号：US20050028118A1
公开(公告)日：2005-02-03
申请号：US10631755
申请日：2003-08-01
申请人： Bhanu Kapoor , Sanjay Churiwala , Joy Banerjee
发明人： Bhanu Kapoor , Sanjay Churiwala , Joy Banerjee
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/505 , G06F2217/62
摘要： Identification and implementation of clock gating in the design of an integrated circuit (IC) is performed with automated assistance. Electrical power consumption is reduced by clock gating. The automated assistance identifies registers that are candidates for clock gating, and highlights, in the IC design, registers associated with a gated clock domain and the logic blocks driven by these registers.
摘要翻译：集成电路（IC）设计中时钟选通的识别和实现是通过自动化辅助进行的。通过时钟门控降低功耗。自动化帮助识别作为时钟门控的候选者的寄存器，并且在IC设计中突出显示与门控时钟域相关联的寄存器以及由这些寄存器驱动的逻辑块。

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