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1. 发明授权

US08410818B1 High speed communication interface with an adaptive swing driver to reduce power consumption 有权
公开(公告)号：US08410818B1
公开(公告)日：2013-04-02
申请号：US13372978
申请日：2012-02-14
申请人： Ying-Yu Hsu , Yung-Chow Peng , Min-Shueh Yuan , Chih-Hsien Chang
发明人： Ying-Yu Hsu , Yung-Chow Peng , Min-Shueh Yuan , Chih-Hsien Chang
IPC分类号： H03K19/094
CPC分类号： H03K3/012 , H03K19/0013 , H03K19/018521
摘要： A high-speed bus interface with an adaptive swing driver. A high speed interface includes a transmitter and a receiver coupled via a bus. The transmitter has an adaptive swing driver and a voltage-regulating-module (VRM). The adaptive swing driver includes a post-driver and a pre-driver. The post-driver provides an adaptive swing output with a dedicated adaptive voltage power supply (VDDQ) and transition emphasis driving capacity with an internal logic voltage supply (VDD). The pre-driver provides the transition emphasis driving capacity with a pull-up and a pull-down signal path to the post-driver. The voltage-regulating-module is configured to supply signal to the adaptive swing driver. The receiver includes a comparator and a bit-error-rate detector. The comparator amplifies the adaptive swing output received from the transmitter via a bus, while the bit-error-rate detector diagnoses the amplified adaptive swing output received from the comparator.

2. 发明授权

US08482332B2 Multi-phase clock generator and data transmission lines 有权
标题翻译：多相时钟发生器和数据传输线
公开(公告)号：US08482332B2
公开(公告)日：2013-07-09
申请号：US13089160
申请日：2011-04-18
申请人： Yung-Chow Peng , Min-Shueh Yuan , Chih-Hsien Chang
发明人： Yung-Chow Peng , Min-Shueh Yuan , Chih-Hsien Chang
IPC分类号： H03K3/00
CPC分类号： H03K5/15066 , H03K5/133 , H03K2005/00058 , H03L7/06
摘要： An embodiment is an integrated circuit. The integrated circuit comprises a clock generator and data transmission lines. The clock generator generates clock signals. At least some of the clock signals have a phase difference from an input clock signal input into the clock generator, and at least some of the clock signals have a different phase difference with respect to at least another of the clock signals. Each of the data transmission lines is triggered at least in part by at least one of the clock signals.
摘要翻译：实施例是集成电路。集成电路包括时钟发生器和数据传输线。时钟发生器产生时钟信号。至少一些时钟信号具有与输入到时钟发生器的输入时钟信号的相位差，并且至少一些时钟信号相对于至少另一个时钟信号具有不同的相位差。至少部分地通过至少一个时钟信号来触发每个数据传输线。

3. 发明申请

US20120262209A1 Multi-Phase Clock Generator and Data Transmission Lines 有权
标题翻译：多相时钟发生器和数据传输线
公开(公告)号：US20120262209A1
公开(公告)日：2012-10-18
申请号：US13089160
申请日：2011-04-18
申请人： Yung-Chow Peng , Min-Shueh Yuan , Chih-Hsien Chang
发明人： Yung-Chow Peng , Min-Shueh Yuan , Chih-Hsien Chang
IPC分类号： H03L7/06 , H03L7/00
CPC分类号： H03K5/15066 , H03K5/133 , H03K2005/00058 , H03L7/06
摘要： An embodiment is an integrated circuit. The integrated circuit comprises a clock generator and data transmission lines. The clock generator generates clock signals. At least some of the clock signals have a phase difference from an input clock signal input into the clock generator, and at least some of the clock signals have a different phase difference with respect to at least another of the clock signals. Each of the data transmission lines is triggered at least in part by at least one of the clock signals.
摘要翻译：实施例是集成电路。集成电路包括时钟发生器和数据传输线。时钟发生器产生时钟信号。至少一些时钟信号具有与输入到时钟发生器的输入时钟信号的相位差，并且至少一些时钟信号相对于至少另一个时钟信号具有不同的相位差。至少部分地通过至少一个时钟信号来触发每个数据传输线。

4. 发明授权

US08519765B2 Method and apparatus for signal phase calibration 有权
标题翻译：用于信号相位校准的方法和装置
公开(公告)号：US08519765B2
公开(公告)日：2013-08-27
申请号：US13228508
申请日：2011-09-09
申请人： Mao-Hsuan Chou , Min-Shueh Yuan , Chih-Hsien Chang
发明人： Mao-Hsuan Chou , Min-Shueh Yuan , Chih-Hsien Chang
IPC分类号： H03H11/16
CPC分类号： H03K5/135 , H03B19/00 , H03L7/099
摘要： A method for signal phase calibration includes providing multiple periodic clock signals, including a reference signal and multiple phase shifted versions of the reference signal. The signals have a common frequency and are shifted from one another by multiples of a phase offset. An edge of a first signal is detected. The first signal is one of multiple phase shifted versions of the reference signal. The edge is a transition from a first logic value to a second logic value. The second logic value of the first signal is compared, upon detection of the edge, to a logic value of a second signal that is one of the first plurality of periodic clock signals other than the first signal. An inversion of the first signal is selectively provided based on an outcome of the comparison.
摘要翻译：用于信号相位校准的方法包括提供多个周期性时钟信号，包括参考信号和参考信号的多个相移版本。这些信号具有共同的频率并且相互偏移倍数的相位偏移。检测到第一信号的边缘。第一个信号是参考信号的多个相移版本之一。边缘是从第一逻辑值到第二逻辑值的转换。第一信号的第二逻辑值在检测到边缘时被比较为除了第一信号之外的第一多个周期性时钟信号之一的第二信号的逻辑值。基于比较的结果选择性地提供第一信号的反转。

5. 发明授权

US09148135B2 Real time automatic and background calibration at embedded duty cycle correlation 有权
标题翻译：嵌入式占空比相关的实时自动和背景校准
公开(公告)号：US09148135B2
公开(公告)日：2015-09-29
申请号：US13532881
申请日：2012-06-26
申请人： Matt Li , Tsung-Hsien Tsai , Mao-Hsuan Chou , Min-Shueh Yuan , Chih-Hsien Chang
发明人： Matt Li , Tsung-Hsien Tsai , Mao-Hsuan Chou , Min-Shueh Yuan , Chih-Hsien Chang
IPC分类号： G06F1/00 , H03K5/156 , G06F1/08
CPC分类号： H03K5/1565 , G06F1/08
摘要： The present disclosure relates to a clock generation system. The system includes a clock source, a tuning buffer, an output buffer, a duty cycle measurement circuit and an automatic calibration component. The clock source generates a clock signal. The tuning buffer is configured to generate a corrected clock signal from the clock signal according to adjustment values. The output buffer is configured to generate an output clock signal from the corrected clock signal. The duty cycle measurement circuit is configured measure a duty cycle of the output clock signal. The automatic calibration component is configured to generate the adjustment values according to the duty cycle measurement and the specification values.
摘要翻译：本公开涉及一种时钟发生系统。该系统包括时钟源，调谐缓冲器，输出缓冲器，占空比测量电路和自动校准部件。时钟源产生时钟信号。调谐缓冲器被配置为根据调整值从时钟信号产生校正的时钟信号。输出缓冲器被配置为从校正的时钟信号产生输出时钟信号。配置占空比测量电路来测量输出时钟信号的占空比。自动校准部件被配置为根据占空比测量值和规格值生成调整值。

6. 发明授权

US08963649B2 PLL with oscillator PVT compensation 有权
标题翻译： PLL振荡器PVT补偿
公开(公告)号：US08963649B2
公开(公告)日：2015-02-24
申请号：US13731687
申请日：2012-12-31
申请人： Matt Li , Min-Shueh Yuan , Chih-Hsien Chang
发明人： Matt Li , Min-Shueh Yuan , Chih-Hsien Chang
IPC分类号： H03L1/00 , H03L7/06 , H03B5/10
CPC分类号： H03L1/00 , H03B5/10 , H03L7/06 , H03L7/099 , H03L7/0992
摘要： A voltage controlled oscillator (VCO) includes a current controlled oscillator, a voltage-to-current converter, and a sensing circuit. The sensing circuit includes a delay unit, and the sensing circuit is configured to generate a plurality of compensation control signals in response to a time delay of the delay unit. The voltage-to-current converter is configured to generate a current signal in response to a VCO control signal and the plurality of compensation control signals. The current controlled oscillator is configured to generate an oscillating signal in response to the current signal.
摘要翻译：压控振荡器（VCO）包括电流控制振荡器，电压 - 电流转换器和感测电路。感测电路包括延迟单元，并且感测电路被配置为响应于延迟单元的时间延迟而产生多个补偿控制信号。电压 - 电流转换器被配置为响应于VCO控制信号和多个补偿控制信号而产生电流信号。电流控制振荡器被配置为响应于当前信号产生振荡信号。

7. 发明申请

US20130342252A1 Real Time Automatic and Background Calibration at Embedded Duty Cycle Correlation 有权
标题翻译：嵌入式占空比相关的实时自动和背景校准
公开(公告)号：US20130342252A1
公开(公告)日：2013-12-26
申请号：US13532881
申请日：2012-06-26
申请人： Matt Li , Tsung-Hsien Tsai , Mao-Hsuan Chou , Min-Shueh Yuan , Chih-Hsien Chang
发明人： Matt Li , Tsung-Hsien Tsai , Mao-Hsuan Chou , Min-Shueh Yuan , Chih-Hsien Chang
IPC分类号： H03K3/017
CPC分类号： H03K5/1565 , G06F1/08
摘要： The present disclosure relates to a clock generation system. The system includes a clock source, a tuning buffer, an output buffer, a duty cycle measurement circuit and an automatic calibration component. The clock source generates a clock signal. The tuning buffer is configured to generate a corrected clock signal from the clock signal according to adjustment values. The output buffer is configured to generate an output clock signal from the corrected clock signal. The duty cycle measurement circuit is configured measure a duty cycle of the output clock signal. The automatic calibration component is configured to generate the adjustment values according to the duty cycle measurement and the specification values.
摘要翻译：本公开涉及一种时钟发生系统。该系统包括时钟源，调谐缓冲器，输出缓冲器，占空比测量电路和自动校准部件。时钟源产生时钟信号。调谐缓冲器被配置为根据调整值从时钟信号产生校正的时钟信号。输出缓冲器被配置为从校正的时钟信号产生输出时钟信号。配置占空比测量电路来测量输出时钟信号的占空比。自动校准部件被配置为根据占空比测量值和规格值生成调整值。

8. 发明授权

US08589831B1 Skew sensitive calculation for misalignment from multi patterning 有权
标题翻译：对多图案化的偏移的偏移计算
公开(公告)号：US08589831B1
公开(公告)日：2013-11-19
申请号：US13561189
申请日：2012-07-30
申请人： Chih-Hsien Chang , Min-Shueh Yuan , Tsung-Hsien Tsai
发明人： Chih-Hsien Chang , Min-Shueh Yuan , Tsung-Hsien Tsai
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Some aspects of the present disclosure provide for a method of accurately simulating variations in an operating parameter, due to processing variations caused by a multi-patterning exposure, by reducing the impact of layout sections having a large width and spacing. The method assigns a skew sensitive index to one or more sections of a multi-patterning layer formed with a first mask. Runlengths of the one or more sections are respectively multiplied by an assigned skew sensitive index to determine a skew variation for each of the one or more sections. The overall skew variation sum is then determined by summing the skew variation for each of the one or more sections. By separately determining the effects of processing variations (e.g., mask misalignment) for different sections of a multi-patterning layer, an accurate measurement of operating parameter variations is achieved.
摘要翻译：本公开的一些方面提供了通过减小具有大的宽度和间隔的布局部分的影响，由于由多图案化曝光引起的处理变化，准确地模拟操作参数的变化的方法。该方法为由形成有第一掩模的多图案化层的一个或多个部分分配偏斜敏感指数。一个或多个部分的运行长度分别乘以一个分配的偏移敏感指数，以确定一个或多个部分中的每个部分的偏斜变化。然后通过对一个或多个部分中的每一个的偏斜变化求和来确定总体偏差变化和。通过分别确定多图案化层的不同部分的处理变化（例如，掩模未对准）的影响，实现了操作参数变化的精确测量。

9. 发明授权

US09229050B2 BIST circuit for phase measurement 有权
标题翻译：用于相位测量的BIST电路
公开(公告)号：US09229050B2
公开(公告)日：2016-01-05
申请号：US13205722
申请日：2011-08-09
申请人： Tsung-Hsien Tsai , Min-Shueh Yuan , Chih-Hsien Chang
发明人： Tsung-Hsien Tsai , Min-Shueh Yuan , Chih-Hsien Chang
IPC分类号： G01R31/3187 , G01R31/30 , G01R31/317
CPC分类号： G01R31/3016 , G01R31/31725 , G01R31/31726 , G01R31/31727 , G01R31/3187
摘要： A BIST circuit for high speed applications includes a phase difference detection circuit, a period-to-current conversion circuit having an input coupled to an output of the phase difference detection circuit and a current-to-voltage conversion circuit coupled to an output of the period-to-current conversion circuit. The phase difference detection circuit includes first NAND logic for receiving as inputs an input clock signal and a delayed version of an inverted version of the input clock signal; second NAND logic for receiving as inputs the inverted version of the input clock signal and a delayed version of the input clock signal; third NAND logic for receiving as inputs the input clock signal and the delayed version of the input clock signal; and fourth NAND logic for receiving as inputs the inverted version of the input clock signal and a delayed version of the inverted version of the input clock signal.
摘要翻译：用于高速应用的BIST电路包括相位差检测电路，具有耦合到相位差检测电路的输出的输入的周期到电流转换电路和耦合到该相位差检测电路的输出的电流 - 电压转换电路周期到电流转换电路。相位差检测电路包括用于接收输入时钟信号和输入时钟信号的反相版本的延迟版本作为输入的第一NAND逻辑; 用于接收输入时钟信号的反相版本和输入时钟信号的延迟版本的第二NAND逻辑; 用于接收输入时钟信号和输入时钟信号的延迟版本作为输入的第三NAND逻辑; 以及用于接收输入时钟信号的反相版本和输入时钟信号的反相版本的延迟版本的第四NAND逻辑。

10. 发明授权

US08510701B2 Over stress verify design rule check 有权
标题翻译：过压力验证设计规则检查
公开(公告)号：US08510701B2
公开(公告)日：2013-08-13
申请号：US13350894
申请日：2012-01-16
申请人： Chen-Ting Ko , Chih-Hsien Chang , Yung-Chow Peng
发明人： Chen-Ting Ko , Chih-Hsien Chang , Yung-Chow Peng
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/78
摘要： Some aspects of this disclosure provide for electronic design automation (EDA) techniques that check whether individual blocks, such as transistors or other semiconductor devices, are connected to their correct power domains during design. In this way, the disclosed EDA techniques can limit or prevent overstress conditions applied to blocks and help to improve reliability of integrated circuits, when manufactured.
摘要翻译：本公开的一些方面提供了电子设计自动化（EDA）技术，其在设计期间检查诸如晶体管或其他半导体器件的各个块是否连接到其正确的电源域。以这种方式，所公开的EDA技术可以限制或防止在制造时应用于块的过应力条件并有助于提高集成电路的可靠性。

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