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1. 发明授权

US08456454B2 Display panel 有权
标题翻译：显示面板
公开(公告)号：US08456454B2
公开(公告)日：2013-06-04
申请号：US12488946
申请日：2009-06-22
申请人： Yung-Chih Chen , Chun-Hsin Liu , Tsung-Ting Tsai , Kuo-Chang Su
发明人： Yung-Chih Chen , Chun-Hsin Liu , Tsung-Ting Tsai , Kuo-Chang Su
IPC分类号： G06F3/038 , G09G5/00 , G02F1/1333
CPC分类号： G09G3/3677 , G09G2300/0426 , G09G2330/08 , G09G2330/12
摘要： A display panel is disclosed, which includes a substrate, a shift register array, plural scan lines, a compensating circuit, a first repair line, and a second repair line. The shift register array having plural shift registers is disposed on a non-display area of the substrate. The scan lines connect to the shift registers respectively to drive plural display units. The first repair line and the second repair line are connected to the compensating circuit and bridged over two ends of each scan line in the non-display area, respectively.
摘要翻译：公开了一种显示面板，其包括基板，移位寄存器阵列，多条扫描线，补偿电路，第一修复线和第二修复线。具有多个移位寄存器的移位寄存器阵列设置在基板的非显示区域上。扫描线分别连接到移位寄存器以驱动多个显示单元。第一修理线和第二修复线分别连接到补偿电路并桥接在非显示区域中的每条扫描线的两端。

2. 发明授权

US08175215B2 Shift register 有权
标题翻译：移位寄存器
公开(公告)号：US08175215B2
公开(公告)日：2012-05-08
申请号：US12572247
申请日：2009-10-01
申请人： Chun-Hsin Liu , Tsung-ting Tsai , Kuo-Chang Su , Yung-Chih Chen
发明人： Chun-Hsin Liu , Tsung-ting Tsai , Kuo-Chang Su , Yung-Chih Chen
IPC分类号： G11C19/00
CPC分类号： G11C19/28
摘要： A shift register includes multiple cascade-connected stages. Each stage generates an output signal in response to a clock signal and a first control signal. Each stage includes a pull-up module, a pull-up driving module, a first pull-down module, a second pull-down module, and a third pull-down module. The pull-up module is used for providing the output signal based on the clock signal. The pull-up driving module turns on the pull-up module in response to a first control signal. The first pull-down module adjusts voltage level on the first node to a first supply voltage in response to a second control signal. The second pull-down module adjusts voltage level on the output end to a second supply voltage in response to the second control signal. The third pull-down module adjusts voltage level on the second node to a third supply voltage in response to a third control signal.
摘要翻译：移位寄存器包括多个级联连接级。每一级响应于时钟信号和第一控制信号产生输出信号。每个级包括上拉模块，上拉驱动模块，第一下拉模块，第二下拉模块和第三下拉模块。上拉模块用于根据时钟信号提供输出信号。上拉驱动模块响应于第一控制信号而导通上拉模块。第一下拉模块响应于第二控制信号将第一节点上的电压电平调整到第一电源电压。第二下拉模块响应于第二控制信号将输出端上的电压电平调整到第二电源电压。第三下拉模块响应于第三控制信号将第二节点上的电压电平调整到第三电源电压。

3. 发明申请

US20110002437A1 SHIFT REGISTERS 有权
标题翻译：移位寄存器
公开(公告)号：US20110002437A1
公开(公告)日：2011-01-06
申请号：US12607156
申请日：2009-10-28
申请人： Kuo-Chang Su , Tsung-Ting Tsai , Yung-Chih Chen , Chun-Hsin Liu
发明人： Kuo-Chang Su , Tsung-Ting Tsai , Yung-Chih Chen , Chun-Hsin Liu
IPC分类号： G11C19/00
CPC分类号： G11C19/28
摘要： A shift register is provided and includes a first shift registering unit and a second shift registering unit. The first shift registering unit generates a first trigger signal at a first output terminal and includes a first pull-down circuit. The second shift registering unit receives the first trigger signal and generates a second trigger signal at a second output terminal. The first trigger signal and the second trigger signal are sequentially asserted. The second shift registering unit includes a second pull-down circuit. The first pull-down circuit and the second pull-down circuit perform pull-down operations at different times. When the first pull-down circuit does not perform the pull-down operation, the second pull-down circuit performs pull-down operations to the first output terminal.
摘要翻译：提供一个移位寄存器，包括一个第一移位寄存单元和一个第二移位寄存单元。第一移位寄存单元在第一输出端产生第一触发信号，并包括第一下拉电路。第二移位寄存单元接收第一触发信号并在第二输出端产生第二触发信号。第一触发信号和第二触发信号被依次断言。第二移位登记单元包括第二下拉电路。第一下拉电路和第二下拉电路在不同时间执行下拉操作。当第一下拉电路不执行下拉操作时，第二下拉电路对第一输出端子执行下拉操作。

4. 发明授权

US08422620B2 Shift registers 有权
标题翻译：移位寄存器
公开(公告)号：US08422620B2
公开(公告)日：2013-04-16
申请号：US12607156
申请日：2009-10-28
申请人： Kuo-Chang Su , Tsung-Ting Tsai , Yung-Chih Chen , Chun-Hsin Liu
发明人： Kuo-Chang Su , Tsung-Ting Tsai , Yung-Chih Chen , Chun-Hsin Liu
IPC分类号： G11C19/00
CPC分类号： G11C19/28
摘要： A shift register is provided and includes a first shift registering unit and a second shift registering unit. The first shift registering unit generates a first trigger signal at a first output terminal and includes a first pull-down circuit. The second shift registering unit receives the first trigger signal and generates a second trigger signal at a second output terminal. The first trigger signal and the second trigger signal are sequentially asserted. The second shift registering unit includes a second pull-down circuit. The first pull-down circuit and the second pull-down circuit perform pull-down operations at different times. When the first pull-down circuit does not perform the pull-down operation, the second pull-down circuit performs pull-down operations to the first output terminal.
摘要翻译：提供一个移位寄存器，包括一个第一移位寄存单元和一个第二移位寄存单元。第一移位寄存单元在第一输出端产生第一触发信号，并包括第一下拉电路。第二移位寄存单元接收第一触发信号并在第二输出端产生第二触发信号。第一触发信号和第二触发信号被依次断言。第二移位登记单元包括第二下拉电路。第一下拉电路和第二下拉电路在不同时间执行下拉操作。当第一下拉电路不执行下拉操作时，第二下拉电路对第一输出端子执行下拉操作。

5. 发明授权

US08581890B2 Liquid crystal display, flat display and gate driving method thereof 有权
标题翻译：液晶显示器，平板显示器及其门驱动方法
公开(公告)号：US08581890B2
公开(公告)日：2013-11-12
申请号：US12684905
申请日：2010-01-09
申请人： Yung-Chih Chen , Tsung-Ting Tsai , Kuo-Chang Su , Chun-Hsin Liu
发明人： Yung-Chih Chen , Tsung-Ting Tsai , Kuo-Chang Su , Chun-Hsin Liu
IPC分类号： G06F3/038
CPC分类号： G09G3/3677 , G09G2310/0251 , G09G2320/0219
摘要： In a liquid crystal display, a flat display and a gate driving method thereof, the flat display comprises first and second pixel rows, first to third gate lines and a gate driving circuit. The first gate line is for determining whether to turn on a portion of pixels in the first pixel row, the second gate line is for determining whether to turn on another portion of pixels in the first pixel row, and the third gate line is for determining whether to turn on a portion of the pixels in the second pixel row. The gate driving circuit is for providing first to third gate driving pulses to the first to third gate lines. The first and second gate driving pulses do not overlap with each other, and the third gate driving pulse partially overlaps with one of the first and second gate driving pulses.
摘要翻译：在液晶显示器，平板显示器及其栅极驱动方法中，平面显示器包括第一和第二像素行，第一至第三栅极线和栅极驱动电路。第一栅极线用于确定是否接通第一像素行中的一部分像素，第二栅极线用于确定是否接通第一像素行中的另一部分像素，并且第三栅极线用于确定是否打开第二像素行中的像素的一部分。栅极驱动电路用于向第一至第三栅极线提供第一至第三栅极驱动脉冲。第一和第二栅极驱动脉冲彼此不重叠，并且第三栅极驱动脉冲与第一和第二栅极驱动脉冲中的一个部分重叠。

6. 发明授权

US08421781B2 Shift register capable of reducing coupling effect 有权
标题翻译：移位寄存器能够减少耦合效应
公开(公告)号：US08421781B2
公开(公告)日：2013-04-16
申请号：US12636801
申请日：2009-12-14
申请人： Yung-Chih Chen , Chun-Hsin Liu , Tsung-Ting Tsai , Kuo-Chang Su
发明人： Yung-Chih Chen , Chun-Hsin Liu , Tsung-Ting Tsai , Kuo-Chang Su
IPC分类号： G06F3/038
CPC分类号： G09G3/3677 , G09G2310/0286 , G09G2320/0209
摘要： A shift register has a plurality of shift register units coupled in series. Each shift register includes a pull-up circuit, an input circuit, a pull-down circuit, a compensation circuit, an input end, an output end and a node. Each shift register unit receives an input voltage at the input end and provides an output voltage at the output end. The input circuit transmits the input voltage to the node based on a first clock signal. The pull-up circuit provides the output voltage based on a second clock signal and the voltage level of the node. The pull-down circuit selectively connects the node with the output end according to a third clock signal. The compensation circuit is coupled to the input circuit, the pull-down circuit and the node for maintaining the voltage level of the node based on the second and third clock signals.
摘要翻译：移位寄存器具有串联耦合的多个移位寄存器单元。每个移位寄存器包括上拉电路，输入电路，下拉电路，补偿电路，输入端，输出端和节点。每个移位寄存器单元在输入端接收输入电压，并在输出端提供输出电压。输入电路基于第一时钟信号将输入电压发送到节点。上拉电路基于第二时钟信号和节点的电压电平提供输出电压。下拉电路根据第三时钟信号选择性地将节点与输出端连接。补偿电路耦合到输入电路，下拉电路和节点，用于基于第二和第三时钟信号来维持节点的电压电平。

7. 发明申请

US20100245298A1 SHIFT REGISTER CAPABLE OF REDUCING COUPLING EFFECT 有权
标题翻译：具有降低耦合效应的移位寄存器
公开(公告)号：US20100245298A1
公开(公告)日：2010-09-30
申请号：US12636801
申请日：2009-12-14
申请人： Yung-Chih Chen , Chun-Hsin Liu , Tsung-Ting Tsai , Kuo-Chang Su
发明人： Yung-Chih Chen , Chun-Hsin Liu , Tsung-Ting Tsai , Kuo-Chang Su
IPC分类号： G06F3/038
CPC分类号： G09G3/3677 , G09G2310/0286 , G09G2320/0209
摘要： A shift register has a plurality of shift register units coupled in series. Each shift register includes a pull-up circuit, an input circuit, a pull-down circuit, a compensation circuit, an input end, an output end and a node. Each shift register unit receives an input voltage at the input end and provides an output voltage at the output end. The input circuit transmits the input voltage to the node based on a first clock signal. The pull-up circuit provides the output voltage based on a second clock signal and the voltage level of the node. The pull-down circuit selectively connects the node with the output end according to a third clock signal. The compensation circuit is coupled to the input circuit, the pull-down circuit and the node for maintaining the voltage level of the node based on the second and third clock signals.
摘要翻译：移位寄存器具有串联耦合的多个移位寄存器单元。每个移位寄存器包括上拉电路，输入电路，下拉电路，补偿电路，输入端，输出端和节点。每个移位寄存器单元在输入端接收输入电压，并在输出端提供输出电压。输入电路基于第一时钟信号将输入电压传输到节点。上拉电路基于第二时钟信号和节点的电压电平提供输出电压。下拉电路根据第三时钟信号选择性地将节点与输出端连接。补偿电路耦合到输入电路，下拉电路和节点，用于基于第二和第三时钟信号来维持节点的电压电平。

8. 发明申请

US20100226473A1 SHIFT REGISTER 有权
标题翻译：移位寄存器
公开(公告)号：US20100226473A1
公开(公告)日：2010-09-09
申请号：US12572247
申请日：2009-10-01
申请人： Chun-Hsin Liu , Tsung-ting Tsai , Kuo-Chang Su , Yung-Chih Chen
发明人： Chun-Hsin Liu , Tsung-ting Tsai , Kuo-Chang Su , Yung-Chih Chen
IPC分类号： G11C19/00
CPC分类号： G11C19/28
摘要： A shift register includes multiple cascade-connected stages. Each stage generates an output signal in response to a clock signal and a first control signal. Each stage includes a pull-up module, a pull-up driving module, a first pull-down module, a second pull-down module, and a third pull-down module. The pull-up module is used for providing the output signal based on the clock signal. The pull-up driving module turns on the pull-up module in response to a first control signal. The first pull-down module adjusts voltage level on the first node to a first supply voltage in response to a second control signal. The second pull-down module adjusts voltage level on the output end to a second supply voltage in response to the second control signal. The third pull-down module adjusts voltage level on the second node to a third supply voltage in response to a third control signal.
摘要翻译：移位寄存器包括多个级联连接级。每一级响应于时钟信号和第一控制信号产生输出信号。每个级包括上拉模块，上拉驱动模块，第一下拉模块，第二下拉模块和第三下拉模块。上拉模块用于根据时钟信号提供输出信号。上拉驱动模块响应于第一控制信号而导通上拉模块。第一下拉模块响应于第二控制信号将第一节点上的电压电平调整到第一电源电压。第二下拉模块响应于第二控制信号将输出端上的电压电平调整到第二电源电压。第三下拉模块响应于第三控制信号将第二节点上的电压电平调整到第三电源电压。

9. 发明申请

US20100171726A1 Display Panel 有权
标题翻译：显示面板
公开(公告)号：US20100171726A1
公开(公告)日：2010-07-08
申请号：US12488946
申请日：2009-06-22
申请人： Yung-Chih Chen , Chun-Hsin Liu , Tsung-Ting Tsai , Kuo-Chang Su
发明人： Yung-Chih Chen , Chun-Hsin Liu , Tsung-Ting Tsai , Kuo-Chang Su
IPC分类号： G06F3/038
CPC分类号： G09G3/3677 , G09G2300/0426 , G09G2330/08 , G09G2330/12
摘要： A display panel is disclosed, which includes a substrate, a shift register array, plural scan lines, a compensating circuit, a first repair line, and a second repair line. The shift register array having plural shift registers is disposed on a non-display area of the substrate. The scan lines connect to the shift registers respectively to drive plural display units. The first repair line and the second repair line are connected to the compensating circuit and bridged over two ends of each scan line in the non-display area, respectively.
摘要翻译：公开了一种显示面板，其包括基板，移位寄存器阵列，多条扫描线，补偿电路，第一修复线和第二修复线。具有多个移位寄存器的移位寄存器阵列设置在基板的非显示区域上。扫描线分别连接到移位寄存器以驱动多个显示单元。第一修理线和第二修复线分别连接到补偿电路并桥接在非显示区域中的每条扫描线的两端。

10. 发明授权

US08027426B1 Shift register 有权
标题翻译：移位寄存器
公开(公告)号：US08027426B1
公开(公告)日：2011-09-27
申请号：US12837244
申请日：2010-07-15
申请人： Yu-Chung Yang , Kuo-Chang Su , Yung-Chih Chen , Chun-Hsin Liu
发明人： Yu-Chung Yang , Kuo-Chang Su , Yung-Chih Chen , Chun-Hsin Liu
IPC分类号： G11C19/00
CPC分类号： G11C19/28 , G09G2310/0286 , G11C19/184
摘要： An exemplary shift register includes a plurality of transistors. The transistors are subjected to the control of a start pulse signal, a first clock signal and a second clock signal to generate a gate driving signal. The first clock signal and the second clock signal are phase-inverted with respect to each other. A logic low level of the first clock signal and another logic low level of the second clock signal are different from each other. Moreover, the transistors are negative threshold voltage transistors. A potential at the gate of the each of the transistors is lower than another potential at the source/drain of the transistor at the situation of the transistor being switched-off state.
摘要翻译：示例性移位寄存器包括多个晶体管。对晶体管进行起始脉冲信号，第一时钟信号和第二时钟信号的控制，以产生栅极驱动信号。第一时钟信号和第二时钟信号相对于彼此相位反相。第一时钟信号的逻辑低电平和第二时钟信号的另一个逻辑低电平彼此不同。而且，晶体管是负阈值电压晶体管。在晶体管处于截止状态的情况下，每个晶体管的栅极处的电位低于晶体管的源极/漏极处的另一个电位。

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