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    • 8. 发明申请
    • SEMICONDUCTOR DEVICE
    • 半导体器件
    • US20120049187A1
    • 2012-03-01
    • US13219662
    • 2011-08-27
    • Masamitsu HARUYAMATatsuhiro SekiDaisuke Arai
    • Masamitsu HARUYAMATatsuhiro SekiDaisuke Arai
    • H01L27/07
    • H01L29/7813H01L29/0619H01L29/0638H01L29/0692H01L29/0696H01L29/407H01L29/66734H01L29/7397H01L29/7808H01L29/7811H01L29/866
    • Accompanying the miniaturization of a gate electrode of a trench gate power MOSFET, the curvature of the bottom part of the trench increases, and thereby, electric fields concentrate on the part and deterioration of a gate oxide film (insulating film) occurs. The deterioration of the gate insulating film is more likely to occur when the gate side bias is negative in the case of an N-channel type power MOSFET and when the gate side bias is positive in the case of a P-channel type power MOSFET.The present invention is a semiconductor device including an insulating gate power transistor etc. in a chip, wherein a gate protection element includes a bidirectional Zener diode and the bidirectional Zener diode has a plurality of P-type impurity regions (or a P-type impurity region) having different concentrations so that the withstand voltage with its gate side negatively biased and the withstand voltage with the gate side positively biased are different from each other.
    • 随着沟槽栅极功率MOSFET的栅电极的小型化,沟槽底部的曲率增加,从而电场集中在该部分上,并且发生栅极氧化膜(绝缘膜)的劣化。 当在N沟道型功率MOSFET的情况下栅极侧偏压为负,并且在P沟道型功率MOSFET的情况下栅极侧偏压为正时,更可能发生栅极绝缘膜的劣化。 本发明是一种在芯片中包括绝缘栅功率晶体管等的半导体器件,其中栅极保护元件包括双向齐纳二极管,双向齐纳二极管具有多个P型杂质区(或P型杂质 区域)具有不同的浓度,使得其栅极侧的耐受电压被负偏置,并且具有正极偏置的栅极侧的耐受电压彼此不同。