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1. 发明授权

US06950360B2 Memory circuit apparatus 失效
标题翻译：存储电路装置
公开(公告)号：US06950360B2
公开(公告)日：2005-09-27
申请号：US10700552
申请日：2003-11-05
申请人： Yukihiro Nishida , Kiyoharu Oikawa
发明人： Yukihiro Nishida , Kiyoharu Oikawa
IPC分类号： G11C16/06 , G11C7/12 , G11C16/04 , G11C7/00
CPC分类号： G11C7/12
摘要： A memory circuit device comprising a plurality of memory cells connected to a plurality of bit lines and word lines, an access circuit connected to the plurality of bit lines and word lines to select predetermined memory cells from the plurality of memory cells in response to an address signal, a precharge circuit which precharges the bit lines connected to the memory cells selected by the access circuit at the time of a read mode, a common source line connected to a plurality of selected memory cells selected by the access circuit, a source line potential control circuit to connect the common source line to a ground node at a predetermined timing, and a discharge circuit which discharges the bit lines connected to non-selected memory cells other than the selected memory cells.
摘要翻译：一种存储器电路装置，包括连接到多个位线和字线的多个存储单元，连接到多个位线和字线的存取电路，以响应于地址从多个存储单元中选择预定存储单元信号，预充电电路，其在读取模式时对连接到由访问电路选择的存储器单元的位线进行预充电，连接到由访问电路选择的多个选择的存储单元的公共源极线，源极线电位控制电路，用于在预定定时将公共源极线连接到接地节点;以及放电电路，其对连接到除所选择的存储器单元之外的未选择的存储器单元进行放电。

2. 发明申请

US20050088877A1 Nonvolatile semiconductor memory device containing reference capacitor circuit 失效
标题翻译：含有参考电容电路的非易失性半导体存储器件
公开(公告)号：US20050088877A1
公开(公告)日：2005-04-28
申请号：US10922906
申请日：2004-08-23
申请人： Kiyoharu Oikawa , Yukihiro Nishida , Masaya Kubota , Junji Morita
发明人： Kiyoharu Oikawa , Yukihiro Nishida , Masaya Kubota , Junji Morita
IPC分类号： G11C16/04 , G11C16/06 , G11C16/28 , G11C17/00 , G11C29/00 , G11C29/04 , H01L21/8247 , H01L27/10 , H01L27/115
CPC分类号： G11C16/28
摘要： A plurality of dummy cells which generate reference potential corresponding to a capacitance of a bit line each have a floating gate, control gate and first and second diffusion layers. The first and second diffusion layers of each dummy cell are commonly connected by use of a wiring.
摘要翻译：产生与位线的电容对应的参考电位的多个虚设单元各自具有浮置栅极，控制栅极和第一和第二扩散层。每个虚拟单元的第一和第二扩散层通过使用布线共同连接。

3. 发明授权

US07167393B2 Nonvolatile semiconductor memory device containing reference capacitor circuit 失效
标题翻译：含有参考电容电路的非易失性半导体存储器件
公开(公告)号：US07167393B2
公开(公告)日：2007-01-23
申请号：US10922906
申请日：2004-08-23
申请人： Kiyoharu Oikawa , Yukihiro Nishida , Masaya Kubota , Junji Morita
发明人： Kiyoharu Oikawa , Yukihiro Nishida , Masaya Kubota , Junji Morita
IPC分类号： G11C16/00
CPC分类号： G11C16/28
摘要： A plurality of dummy cells which generate reference potential corresponding to a capacitance of a bit line each have a floating gate, control gate and first and second diffusion layers. The first and second diffusion layers of each dummy cell are commonly connected by use of a wiring.
摘要翻译：产生与位线的电容对应的参考电位的多个虚设单元各自具有浮置栅极，控制栅极和第一和第二扩散层。每个虚拟单元的第一和第二扩散层通过使用布线共同连接。

4. 发明授权

US06643203B2 Semiconductor memory device including clock-independent sense amplifier 失效
公开(公告)号：US06643203B2
公开(公告)日：2003-11-04
申请号：US10230229
申请日：2002-08-29
申请人： Kiyoharu Oikawa , Kimio Maruyama , Yasuhiro Watanabe , Naokazu Kuzuno
发明人： Kiyoharu Oikawa , Kimio Maruyama , Yasuhiro Watanabe , Naokazu Kuzuno
IPC分类号： G11C702
CPC分类号： G11C29/025 , G11C7/06 , G11C16/28 , G11C29/02 , G11C2207/005
摘要： A semiconductor memory device includes a memory cell array, a read control circuit, a row decoder, a column decoder, a sense amplifier, and a sense amplifier control circuit. The read control circuit produces a precharge signal to precharge a bit line of the memory cell array. The sense amplifier amplifies data read onto the bit line. In reading data from a memory cell, the sense amplifier control circuit enables the sense amplifier and inhibits entry of read data from a memory cell into the sense amplifier only for a fixed interval after a fixed time after the precharging signal has been negated. The sense amplifier control circuit allows entry of read data into the sense amplifier while the sense amplifier is being disabled.

5. 发明授权

US06459157B1 Semiconductor device and double-sided multi-chip package 失效
标题翻译：半导体器件和双面多芯片封装
公开(公告)号：US06459157B1
公开(公告)日：2002-10-01
申请号：US09487674
申请日：2000-01-20
申请人： Kiyoharu Oikawa
发明人： Kiyoharu Oikawa
IPC分类号： H01L2704
CPC分类号： H01L24/06 , H01L23/50 , H01L23/5386 , H01L24/48 , H01L24/49 , H01L25/0657 , H01L2224/05554 , H01L2224/05599 , H01L2224/0603 , H01L2224/48227 , H01L2224/49171 , H01L2224/85399 , H01L2225/0651 , H01L2225/06527 , H01L2225/06572 , H01L2924/00014 , H01L2924/12041 , H01L2924/30105 , H01L2224/45099 , H01L2924/00
摘要： A semiconductor device has a circuit board, a main chip mounted on a first surface of the circuit board, a subchip mounted on a second surface of the circuit board, interface circuits distributed in the main chip along four sides of the main chip, respectively, to interface the main chip and the subchip with each other, subchip connecting terminals for connecting the interface circuits and the subchip to each other through the circuit board, main-chip connecting terminals for connecting the main chip and the outside to each other, subchip bonding terminals connected to the subchip, a first wiring area for connecting the subchip bonding terminals and the subchip connecting terminals to each other, package terminals for connecting the main chip and the outside to each other, and a second wiring area for connecting the package terminals and the main-chip connecting terminals to each other.
摘要翻译：半导体器件具有电路板，安装在电路板的第一表面上的主芯片，安装在电路板的第二表面上的子芯片，分别沿着主芯片的四个侧面分布在主芯片中的接口电路，将主芯片和子芯片彼此接合，用于通过电路板将接口电路和子芯片彼此连接的子芯片连接端子，用于将主芯片和外部连接的主芯片连接端子彼此连接，子芯片接合连接到子芯片的端子，用于将子芯片接合端子和子芯片连接端子彼此连接的第一布线区域，用于将主芯片和外部彼此连接的封装端子和用于将封装端子和主芯片连接端子彼此。

6. 发明授权

US07260012B2 Fuse latch circuit 失效
标题翻译：保险丝锁存电路
公开(公告)号：US07260012B2
公开(公告)日：2007-08-21
申请号：US10777971
申请日：2004-02-13
申请人： Naokazu Kuzuno , Kimio Maruyama , Yasuhiro Hegi , Kiyoharu Oikawa
发明人： Naokazu Kuzuno , Kimio Maruyama , Yasuhiro Hegi , Kiyoharu Oikawa
IPC分类号： G11C17/18
CPC分类号： G11C17/18
摘要： One end of a fuse is connected to a ground point via a transistor N1A, and the other end thereof is connected to a node VaA. For example, at a fuse connection case, when INTV=“H” is input to the gate of the transistor N1A, the node VaA becomes “L.” At INTV=“L”, a transistor P1A having a low “on” resistance turns ON, and the node VaA is quickly precharged. At INTV=“H”, the transistor N1A turns ON, and the node VaA is quickly discharged.
摘要翻译：保险丝的一端通过晶体管N1A连接到接地点，另一端连接到节点VaA。例如，在熔丝连接情况下，当INTV =“H”被输入到晶体管N1A的栅极时，节点VaA变为“L”。在INTV =“L”时，具有低“导通”电阻的晶体管P1A导通，并且节点VaA被快速预充电。在INTV =“H”时，晶体管N 1A导通，节点VaA快速放电。

7. 发明申请

US20060245289A1 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US20060245289A1
公开(公告)日：2006-11-02
申请号：US11412122
申请日：2006-04-27
申请人： Kiyoharu Oikawa
发明人： Kiyoharu Oikawa
IPC分类号： G11C5/14
CPC分类号： G11C16/24
摘要： A semiconductor integrated circuit has a sense amplifier which senses and outputs data read out from memory cells connected to word lines and bit lines, and a read-out control circuit which has a standby state consuming minimum necessary power and a read state reading out the memory cells, and controls read-out of the memory cells, wherein the read-out control circuit includes, a bit line switching circuit which switches whether or not to transmit a potential on the bit line to an input terminal of the sense amplifier, and a first switching control circuit which controls the bit line switching circuit to prevent the potential on the bit line from being transmitted to the input terminal of the sense amplifier during a period of the standby state and a predetermined period after the standby state is released.
摘要翻译：半导体集成电路具有感测放大器，其感测并输出从连接到字线和位线的存储单元读出的数据;以及读出控制电路，其具有消耗最小必需功率的待机状态和读取存储器的读取状态单元并且控制读出存储单元，其中读出控制电路包括位线切换电路，其切换是否将位线上的电位传输到读出放大器的输入端，以及第一切换控制电路，其控制位线切换电路，以防止在待机状态期间和待机状态被释放之后的预定时间段内位线上的电位被发送到读出放大器的输入端。

8. 发明授权

US07598791B2 Semiconductor integrated apparatus using two or more types of power supplies 失效
标题翻译：使用两种以上电源的半导体集成装置
公开(公告)号：US07598791B2
公开(公告)日：2009-10-06
申请号：US11564603
申请日：2006-11-29
申请人： Kiyoharu Oikawa
发明人： Kiyoharu Oikawa
IPC分类号： H03L5/00
CPC分类号： H03K3/356008 , H03K3/356182
摘要： A semiconductor integrated apparatus includes a control circuit unit which is connected to a low potential power supply terminal and a ground potential power supply terminal, and to which a predetermined low potential power supply output is supplied via the low potential power supply terminal, an output circuit unit which is connected to a high potential power supply terminal and the ground potential power supply terminal, and to which an output from the control circuit unit is supplied, and a detection circuit unit which is connected to the low potential power supply terminal, and which detects a decline in the predetermined low potential power supply output. The apparatus further includes a level shifter circuit which is provided between the control circuit unit and the output circuit unit, and which controls an output level of the output circuit unit in accordance with a detected output from the detection circuit unit.
摘要翻译：一种半导体集成装置，包括：连接到低电位电源端子和地电位电源端子的控制电路单元，经由低电位电源端子向其提供预定的低电位电源输出;输出电路连接到高电位电源端子和地电位电源端子的单元，并且连接到低电位电源端子的与控制电路单元的输出端相连的检测电路单元，以及哪个检测预定的低电位电源输出的下降。该装置还包括电平移位器电路，其设置在控制电路单元和输出电路单元之间，并根据检测电路单元的检测输出来控制输出电路单元的输出电平。

9. 发明申请

US20070120577A1 SEMICONDUCTOR INTEGRATED APPARATUS USING TWO OR MORE TYPES OF POWER SUPPLIES 失效
标题翻译：使用两种或多种电源的半导体集成装置
公开(公告)号：US20070120577A1
公开(公告)日：2007-05-31
申请号：US11564603
申请日：2006-11-29
申请人： Kiyoharu Oikawa
发明人： Kiyoharu Oikawa
IPC分类号： H03K19/0175
CPC分类号： H03K3/356008 , H03K3/356182
摘要： A semiconductor integrated apparatus includes a control circuit unit which is connected to a low potential power supply terminal and a ground potential power supply terminal, and to which a predetermined low potential power supply output is supplied via the low potential power supply terminal, an output circuit unit which is connected to a high potential power supply terminal and the ground potential power supply terminal, and to which an output from the control circuit unit is supplied, and a detection circuit unit which is connected to the low potential power supply terminal, and which detects a decline in the predetermined low potential power supply output. The apparatus further includes a level shifter circuit which is provided between the control circuit unit and the output circuit unit, and which controls an output level of the output circuit unit in accordance with a detected output from the detection circuit unit.
摘要翻译：一种半导体集成装置，包括：连接到低电位电源端子和地电位电源端子的控制电路单元，经由低电位电源端子向其提供预定的低电位电源输出;输出电路连接到高电位电源端子和地电位电源端子的单元，并且连接到低电位电源端子的与控制电路单元的输出端相连的检测电路单元，以及哪个检测预定的低电位电源输出的下降。该装置还包括电平移位器电路，其设置在控制电路单元和输出电路单元之间，并根据检测电路单元的检测输出来控制输出电路单元的输出电平。

10. 发明授权

US07123527B2 Redundancy fuse circuit 失效
标题翻译：冗余保险丝电路
公开(公告)号：US07123527B2
公开(公告)日：2006-10-17
申请号：US10803936
申请日：2004-03-19
申请人： Naokazu Kuzuno , Kiyoharu Oikawa , Kimio Maruyama , Yasuhiro Watanabe , Masaya Kubota
发明人： Naokazu Kuzuno , Kiyoharu Oikawa , Kimio Maruyama , Yasuhiro Watanabe , Masaya Kubota
IPC分类号： G11C7/00
CPC分类号： G11C29/24 , G11C29/02 , G11C29/027 , G11C29/78
摘要： A redundancy fuse circuit including a function of replacing a defective cell in a memory cell array with a redundancy cell, comprising a fuse circuit in which an address of the defective cell or a block including the defective cell is programmed as a defective address by presence/absence of cut-off of a fuse, a data latch circuit which latches a signal supplied from a tester to program the defective address in a dummy manner, and a comparator which replaces the defective cell with the redundancy cell based on an address signal supplied from the tester and an output signal of the data latch circuit at an operation confirmation time of the redundancy fuse circuit.
摘要翻译：一种冗余熔丝电路，包括用冗余单元替换存储单元阵列中的有缺陷单元的功能，包括熔丝电路，其中有缺陷单元的地址或包括有缺陷单元的块被编程为有缺陷地址，不存在保险丝的截止，锁存从测试器提供的信号以虚拟方式对缺陷地址进行编程的数据锁存电路，以及基于从冗余单元提供的地址信号替换缺陷单元的比较器测试器和数据锁存电路的输出信号在冗余熔丝电路的操作确认时间。

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