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1. 发明申请

US20140231827A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20140231827A1
公开(公告)日：2014-08-21
申请号：US14141174
申请日：2013-12-26
申请人： Yukihiko WATANABE , Sachiko AOI , Masahiro SUGIMOTO , Akitaka SOENO , Shinichiro MIYAHARA
发明人： Yukihiko WATANABE , Sachiko AOI , Masahiro SUGIMOTO , Akitaka SOENO , Shinichiro MIYAHARA
IPC分类号： H01L29/47 , H01L29/45 , H01L29/16 , H01L21/285 , H01L29/78
CPC分类号： H01L29/47 , H01L21/0485 , H01L21/28518 , H01L29/1608 , H01L29/45 , H01L29/66068 , H01L29/78 , H01L29/7806 , H01L29/7813
摘要： A method of manufacturing a semiconductor device includes forming an ohmic electrode in a first area on one of main surfaces of a silicon carbide layer, siliciding the ohmic electrode, and forming a Schottky electrode in a second area on the one of the main surfaces of the silicon carbide layer with self alignment. The second area is exposed where the ohmic electrode is not formed.
摘要翻译：一种制造半导体器件的方法包括：在碳化硅层的一个主表面上的第一区域中形成欧姆电极，将欧姆电极硅化，并在第二区域中形成肖特基电极具有自对准的碳化硅层。在没有形成欧姆电极的情况下暴露第二区域。

2. 发明申请

US20120161154A1 SILICON CARBIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME 有权
标题翻译：硅碳化硅半导体器件及其制造方法
公开(公告)号：US20120161154A1
公开(公告)日：2012-06-28
申请号：US13330835
申请日：2011-12-20
申请人： Tomohiro MIMURA , Shinichiro MIYAHARA , Hidefumi TAKAYA , Masahiro SUGIMOTO , Narumasa SOEJIMA , Tsuyoshi ISHIKAWA , Yukihiko WATANABE
发明人： Tomohiro MIMURA , Shinichiro MIYAHARA , Hidefumi TAKAYA , Masahiro SUGIMOTO , Narumasa SOEJIMA , Tsuyoshi ISHIKAWA , Yukihiko WATANABE
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/045 , H01L29/1608 , H01L29/4236 , H01L29/42368 , H01L29/66068 , H01L29/7397
摘要： An SiC semiconductor device includes a substrate, a drift layer, a base region, a source region, a trench, a gate oxide film, a gate electrode, a source electrode and a drain electrode. The substrate has a Si-face as a main surface. The source region has the Si-face. The trench is provided from a surface of the source region to a portion deeper than the base region and extends longitudinally in one direction and has a Si-face bottom. The trench has an inverse tapered shape, which has a smaller width at an entrance portion than at a bottom, at least at a portion that is in contact with the base region.
摘要翻译： SiC半导体器件包括衬底，漂移层，基极区域，源极区域，沟槽，栅极氧化膜，栅电极，源电极和漏电极。基板具有作为主表面的Si面。源区具有Si面。沟槽从源极区域的表面提供到比基部区域更深的部分并且在一个方向上纵向延伸并且具有Si面底部。沟槽具有倒锥形形状，至少在与基部区域接触的部分处，入口部分处的宽度比底部宽。

3. 发明申请

US20120273801A1 SILICON CARBIDE SEMICONDUCTOR DEVICE 有权
标题翻译：硅碳化硅半导体器件
公开(公告)号：US20120273801A1
公开(公告)日：2012-11-01
申请号：US13450639
申请日：2012-04-19
申请人： Hiroki WATANABE , Shinichiro MIYAHARA , Masahiro SUGIMOTO , Hidefumi TAKAYA , Yukihiko WATANABE , Narumasa SOEJIMA , Tsuyoshi ISHIKAWA
发明人： Hiroki WATANABE , Shinichiro MIYAHARA , Masahiro SUGIMOTO , Hidefumi TAKAYA , Yukihiko WATANABE , Narumasa SOEJIMA , Tsuyoshi ISHIKAWA
IPC分类号： H01L29/24
CPC分类号： H01L29/7813 , H01L29/045 , H01L29/0634 , H01L29/1095 , H01L29/1608 , H01L29/66068 , H01L29/7397
摘要： A SiC semiconductor device includes: a SiC substrate including a first or second conductive type layer and a first conductive type drift layer and including a principal surface having an offset direction; a trench disposed on the drift layer and having a longitudinal direction; and a gate electrode disposed in the trench via a gate insulation film. A sidewall of the trench provides a channel formation surface. The vertical semiconductor device flows current along with the channel formation surface of the trench according to a gate voltage applied to the gate electrode. The offset direction of the SiC substrate is perpendicular to the longitudinal direction of the trench.
摘要翻译： SiC半导体器件包括：SiC衬底，包括第一或第二导电类型层和第一导电类型漂移层，并且包括具有偏移方向的主表面; 设置在所述漂移层上并具有纵向方向的沟槽; 以及通过栅极绝缘膜设置在沟槽中的栅电极。沟槽的侧壁提供通道形成表面。垂直半导体器件根据施加到栅电极的栅极电压与沟道形成表面一起流动电流。 SiC衬底的偏移方向垂直于沟槽的纵向方向。

4. 发明申请

US20170084735A1 SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME 审中-公开
公开(公告)号：US20170084735A1
公开(公告)日：2017-03-23
申请号：US15365150
申请日：2016-11-30
申请人： Masahiro SUGIMOTO , Hidefumi TAKAYA , Akitaka SOENO , Jun MORIMOTO , DENSO CORPORATION , TOYOTA JIDOSHA KABUSHIKI KAISHA
发明人： Yuichi TAKEUCHI , Naohiro SUZUKI , Masahiro SUGIMOTO , Hidefumi TAKAYA , Akitaka SOENO , Jun MORIMOTO , Narumasa SOEJIMA , Yukihiko WATANABE
IPC分类号： H01L29/78 , H01L29/16 , H01L29/06 , H01L21/04 , H01L29/66 , H01L29/417 , H01L29/872 , H01L29/15 , H01L21/761
CPC分类号： H01L29/7811 , H01L21/046 , H01L21/0475 , H01L21/30604 , H01L21/308 , H01L21/761 , H01L21/8213 , H01L29/0615 , H01L29/063 , H01L29/0634 , H01L29/0661 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/157 , H01L29/158 , H01L29/1608 , H01L29/41766 , H01L29/4236 , H01L29/66068 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7813 , H01L29/861 , H01L29/872
摘要： An SiC semiconductor device has a p type region including a low concentration region and a high concentration region filled in a trench formed in a cell region. A p type column is provided by the low concentration region, and a p+ type deep layer is provided by the high concentration region. Thus, since a SJ structure can be made by the p type column and the n type column provided by the n type drift layer, an on-state resistance can be reduced. As a drain potential can be blocked by the p+ type deep layer, at turnoff, an electric field applied to the gate insulation film can be alleviated and thus breakage of the gate insulation film can be restricted. Therefore, the SiC semiconductor device can realize the reduction of the on-state resistance and the restriction of breakage of the gate insulation film.

5. 发明申请

US20110291110A1 SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：硅碳化硅半导体器件及其制造方法
公开(公告)号：US20110291110A1
公开(公告)日：2011-12-01
申请号：US13117575
申请日：2011-05-27
申请人： Naohiro SUZUKI , Hideo MATSUKI , Masahiro SUGIMOTO , Hidefumi TAKAYA , Jun MORIMOTO , Tsuyoshi ISHIKAWA , Narumasa SOEJIMA , Yukihiko WATANABE
发明人： Naohiro SUZUKI , Hideo MATSUKI , Masahiro SUGIMOTO , Hidefumi TAKAYA , Jun MORIMOTO , Tsuyoshi ISHIKAWA , Narumasa SOEJIMA , Yukihiko WATANABE
IPC分类号： H01L29/12 , H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/66068
摘要： The silicon carbide semiconductor device includes a substrate, a drift layer, a base region, a source region, a trench, a gate insulating layer, a gate electrode, a source electrode, a drain electrode, and a deep layer. The deep layer is disposed under the base region and is located to a depth deeper than the trench. The deep layer is divided into a plurality of portions in a direction that crosses a longitudinal direction of the trench. The portions include a group of portions disposed at positions corresponding to the trench and arranged at equal intervals in the longitudinal direction of the trench. The group of portions surrounds corners of a bottom of the trench.
摘要翻译：碳化硅半导体器件包括衬底，漂移层，基极区域，源极区域，沟槽，栅极绝缘层，栅极电极，源极电极，漏极电极和深层。深层设置在基底区域下方并且位于比沟槽更深的深度。深层在与沟槽的纵向方向交叉的方向上分成多个部分。这些部分包括设置在与沟槽相对应的位置处的一组部分，其在沟槽的纵向方向上以相等的间隔布置。该组部分围绕沟槽的底部的角落。

6. 发明申请

US20120142173A1 MANUFACTURING METHOD OF SILICON CARBIDE SINGLE CRYSTAL 有权
标题翻译：碳化硅单晶的制造方法
公开(公告)号：US20120142173A1
公开(公告)日：2012-06-07
申请号：US13308721
申请日：2011-12-01
申请人： Hiroki WATANABE , Yasuo KITOU , Yasushi FURUKAWA , Kensaku YAMAMOTO , Hidefumi TAKAYA , Masahiro SUGIMOTO , Yukihiko WATANABE , Narumasa SOEJIMA , Tsuyoshi ISHIKAWA
发明人： Hiroki WATANABE , Yasuo KITOU , Yasushi FURUKAWA , Kensaku YAMAMOTO , Hidefumi TAKAYA , Masahiro SUGIMOTO , Yukihiko WATANABE , Narumasa SOEJIMA , Tsuyoshi ISHIKAWA
IPC分类号： H01L21/20 , C30B25/20 , C30B25/02
CPC分类号： H01L21/0262 , C30B25/186 , C30B29/36 , H01L21/02378 , H01L21/0243 , H01L21/02529 , H01L21/02658 , H01L21/046 , H01L21/0475 , H01L29/04
摘要： A manufacturing method of an SiC single crystal includes preparing an SiC substrate, implanting ions into a surface portion of the SiC substrate to form an ion implantation layer, activating the ions implanted into the surface portion of the SiC substrate by annealing, chemically etching the surface portion of the SiC substrate to form an etch pit that is caused by a threading screw dislocation included in the SiC substrate and performing an epitaxial growth of SiC to form an SiC growth layer on a surface of the SiC substrate including an inner wall of the etch pit in such a manner that portions of the SiC growth layer grown on the inner wall of the etch pit join with each other.
摘要翻译： SiC单晶的制造方法包括制备SiC衬底，将离子注入到SiC衬底的表面部分中以形成离子注入层，通过退火激活注入到SiC衬底的表面部分中的离子，化学蚀刻表面以形成由SiC衬底中的螺纹位错引起的蚀刻坑，并且在SiC衬底的表面上进行SiC的外延生长以形成SiC生长层，所述SiC生长层包括蚀刻的内壁以使得在蚀刻坑的内壁上生长的SiC生长层的部分彼此连接的方式形成凹坑。

7. 发明申请

US20080105903A1 Group III nitride based semiconductor and production method therefor 有权
标题翻译： III族氮化物基半导体及其制备方法
公开(公告)号：US20080105903A1
公开(公告)日：2008-05-08
申请号：US11976450
申请日：2007-10-24
申请人： Masahito KODAMA , Eiko HAYSASHI , Masahiro SUGIMOTO
发明人： Masahito KODAMA , Eiko HAYSASHI , Masahiro SUGIMOTO
IPC分类号： H01L29/205 , H01L29/20 , H01L21/20
CPC分类号： H01L21/02433 , H01L21/0242 , H01L21/02458 , H01L21/0254 , H01L21/02639 , H01L21/0265
摘要： The invention provides a method for producing a group III nitride based semiconductor having a reduced number of crystal defects. A GaN layer 2 is epitaxially grown on a sapphire substrate 1 having C-plane as a main plane (FIG. 1A). Then, the layer is wet-etched by use of a 25% aqueous TMAH solution at 85° C. for one hour, to thereby form an etch pit 4 (FIG. 1B) Then, a GaN layer 5 is grown on the GaN layer 2 through the ELO method (FIG. 1C). The thus-formed GaN layer 5 has a screw dislocation density lower than that of the GaN layer 2.
摘要翻译：本发明提供一种具有减少晶体缺陷数的III族氮化物基半导体的制造方法。在具有C面作为主平面的蓝宝石衬底1上外延生长GaN层2（图1A）。然后，通过在85℃下使用25％TMAH水溶液湿法蚀刻该层1小时，从而形成蚀刻坑4（图1B）然后，在GaN上生长GaN层5 层2通过ELO方法（图1C）。如此形成的GaN层5的螺旋位错密度低于GaN层2的位错密度。

8. 发明申请

US20140319577A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20140319577A1
公开(公告)日：2014-10-30
申请号：US14244038
申请日：2014-04-03
申请人： Masahiro SUGIMOTO , Yuichi Takeuchi
发明人： Masahiro SUGIMOTO , Yuichi Takeuchi
IPC分类号： H01L29/739 , H01L29/66
CPC分类号： H01L29/7397 , H01L29/1095 , H01L29/1608 , H01L29/2003 , H01L29/36 , H01L29/4236 , H01L29/66348 , H01L29/7789
摘要： A semiconductor device disclosed in this specification includes a p+ contact region, an n+ source region, a p− base region, an n− drift region, a gate electrode, an insulator, a p+ electric field alleviating layer, and a p− positive hole extraction region. The electric field alleviating layer has same impurity concentration as the base region or higher, contacts a lower surface of the base region, and is formed in a same depth as the gate trench or in a position deeper than the gate trench. A positive hole extraction region extends to contact the electric field alleviating layer from a position to contact an upper surface of a semiconductor substrate or a first semiconductor region, and extracts a positive hole that is produced in the electric field alleviating layer at the avalanche breakdown to the upper surface of the semiconductor substrate.
摘要翻译：在本说明书中公开的半导体装置包括p +接触区域，n +源极区域，基极区域，n漂移区域，栅电极，绝缘体，p +电场缓和层和ap-空穴提取区域。电场缓和层具有与基底区域相同的杂质浓度或更高的接触基底区域的下表面，并且形成在与栅极沟槽相同的深度或比栅极沟槽更深的位置。正空穴提取区域延伸以从与半导体衬底或第一半导体区域的上表面接触的位置接触电场缓和层，并且在雪崩击穿时提取在电场减轻层中产生的正空穴半导体衬底的上表面。

9. 发明申请

US20140319540A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20140319540A1
公开(公告)日：2014-10-30
申请号：US14258251
申请日：2014-04-22
申请人： Masahiro SUGIMOTO
发明人： Masahiro SUGIMOTO
IPC分类号： H01L27/16
CPC分类号： H01L29/0653 , H01L29/0623 , H01L29/0696 , H01L29/1608 , H01L29/32 , H01L29/407 , H01L29/42368 , H01L29/66068 , H01L29/7397 , H01L29/7804
摘要： A semiconductor device is provided with a semiconductor substrate in which a power semiconductor element part and a temperature sensing diode part are provided. The temperature sensing diode part includes a first semiconductor region, a second semiconductor region, a first base region, and a first drift region. In the semiconductor substrate, an isolation trench is formed, which passes through the first base region, extends to the first drift region, and surrounds an outer periphery of the temperature sensing diode part. At least a part of one of side walls of the isolation trench is in contact with the power semiconductor element part, and the other side wall of the isolation trench is in contact with the temperature sensing diode part.
摘要翻译：半导体器件设置有半导体衬底，其中提供功率半导体元件部分和温度感测二极管部分。温度感测二极管部分包括第一半导体区域，第二半导体区域，第一基极区域和第一漂移区域。在半导体衬底中，形成隔离沟槽，其通过第一基极区域延伸到第一漂移区域并且包围温度感测二极管部件的外周。隔离沟槽的一个侧壁的至少一部分与功率半导体元件部分接触，并且隔离沟槽的另一个侧壁与温度感测二极管部分接触。

10. 发明申请

US20100295098A1 III-V HEMT DEVICES 有权
标题翻译： III-V HEMT设备
公开(公告)号：US20100295098A1
公开(公告)日：2010-11-25
申请号：US12822328
申请日：2010-06-24
申请人： Masahiro SUGIMOTO , Tetsu KACHI , Yoshitaka NAKANO , Tsutomu UESUGI , Hiroyuki UEDA , Narumasa SOEJIMA
发明人： Masahiro SUGIMOTO , Tetsu KACHI , Yoshitaka NAKANO , Tsutomu UESUGI , Hiroyuki UEDA , Narumasa SOEJIMA
IPC分类号： H01L29/778 , H01L21/335
CPC分类号： H01L29/778 , H01L21/28 , H01L29/2003 , H01L29/66431 , H01L29/66462 , H01L29/7787
摘要： A semiconductor device has a stacked structure in which a p-GaN layer, an SI-GaN layer, and an AlGaN layer are stacked, and has a gate electrode that is formed at a top surface side of the AlGaN layer. A band gap of the AlGaN layer is wider than a band gap of the p-GaN layer and the SI-GaN layer. Moreover, impurity concentration of the SI-GaN layer is less than 1×1017 cm−3. Semiconductor devices including III-V semiconductors may have a stable normally-off operation.
摘要翻译：半导体器件具有其中堆叠p-GaN层，SI-GaN层和AlGaN层的堆叠结构，并且具有形成在AlGaN层的顶表面侧的栅电极。 AlGaN层的带隙比p-GaN层和SI-GaN层的带隙宽。此外，SI-GaN层的杂质浓度小于1×1017cm-3。包括III-V半导体的半导体器件可以具有稳定的常关断操作。

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