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    • 2. 发明授权
    • Digital image forming apparatus with test image optimization
    • 具有测试图像优化的数字图像形成装置
    • US5822079A
    • 1998-10-13
    • US611814
    • 1996-03-06
    • Yukihiko OkunoToshifumi WatanabeKentaro Katori
    • Yukihiko OkunoToshifumi WatanabeKentaro Katori
    • G03G15/01G03G15/00H04N1/29H04N1/407G03G21/00
    • G03G15/5041G03G2215/00042G03G2215/00063G03G2215/00084
    • An image forming apparatus is provided which is immune to characteristic variations of a photoconductor and a developer material, which can detect the amount of toner adhering to a test toner image accurately, and which can always form a favorable image using an optimal image forming parameter. A predetermined test toner image is formed on the photoconductor using developing devices. The amount of toner adhering to the formed test toner image is detected by an AIDC sensor. A printer control unit determines grid potential Vg of a corona charger and development bias potential Vb of each developing device based on the detected amount of adhering toner. A predetermined image is formed using the determined grid potential and development bias potential. The printer control unit changes the image forming condition for the next test toner image based on the detected amount of adhering toner so that the amount of toner adhering to the next test toner image can be detected in a range of high detection sensitivity of the AIDC sensor.
    • 提供了一种图像形成装置,其不受光电导体和显影剂材料的特征变化的影响,可以精确地检测附着在测试调色剂图像上的调色剂的量,并且可以始终使用最佳图像形成参数形成良好的图像。 使用显影装置在感光体上形成预定的测试调色剂图像。 通过AIDC传感器检测附着在形成的测试调色剂图像上的调色剂的量。 打印机控制单元基于检测到的粘附调色剂量来确定电晕充电器的电网电位Vg和显影装置的显影偏压电位Vb。 使用确定的电网电位和显影偏压电位形成预定图像。 打印机控制单元基于检测到的粘附调色剂量来改变下一个测试调色剂图像的图像形成条件,使得可以在AIDC传感器的高检测灵敏度的范围内检测粘附到下一个测试调色剂图像的调色剂的量 。
    • 5. 发明授权
    • Tandem-type image forming apparatus and image forming condition
determination method used in this tandem-type image forming apparatus
    • 串联式图像形成装置和图像形成条件确定方法,用于该串列型图像形成装置
    • US5978615A
    • 1999-11-02
    • US162222
    • 1998-09-28
    • Masaki TanakaYukihiko OkunoToshifumi Watanabe
    • Masaki TanakaYukihiko OkunoToshifumi Watanabe
    • G03G15/00G03G15/01G03G15/16G03G15/14
    • G03G15/5062G03G15/0194G03G15/5058G03G2215/00059G03G2215/00063G03G2215/00067G03G2215/0119
    • Using an image forming apparatus, toner images are respectively formed on photosensitive drums of image forming units set along a transport belt, and the toner images are transferred onto the transport belt or a recording sheet transported on the transport belt to form a color image. The image forming apparatus is composed of a first density detecting sensor for detecting a density of a toner image formed on the recording sheet or the transport belt at the upstream side of each transfer position of at least one image forming unit which is located at the downstream side of a first image forming unit in a transport direction of the transport belt and which is selected as a subject of an image forming condition determination, a second density detecting sensor for detecting a density of the toner image formed on the recording sheet or the transport belt at the downstream side of the transfer position, and an image forming condition determining unit for comparing a detection value given by the first density detecting sensor with a detection value given by the second density detecting sensor and for determining an image forming condition in accordance with the comparison result for an image formation performed by the image forming unit selected as the subject.
    • 使用图像形成装置,将调色剂图像分别形成在沿着传送带设置的图像形成单元的感光鼓上,并且将调色剂图像转印到在传送带上传送的传送带或记录片材上以形成彩色图像。 图像形成装置由用于检测在位于下游的至少一个图像形成单元的每个转印位置的上游侧的记录纸或输送带上形成的调色剂图像的浓度的第一浓度检测传感器 在输送带的运送方向上的第一图像形成单元的侧面,并且被选择为图像形成条件确定的对象;第二密度检测传感器,用于检测形成在记录片材上的调色剂图像的浓度或运送 皮带在转印位置的下游侧,以及图像形成条件确定单元,用于将由第一密度检测传感器给出的检测值与由第二密度检测传感器给出的检测值进行比较,并且用于根据 由作为对象选择的图像形成单元执行的图像形成的比较结果。
    • 6. 发明授权
    • Semiconductor memory device
    • 半导体存储器件
    • US08223569B2
    • 2012-07-17
    • US12836851
    • 2010-07-15
    • Tomoyuki HamanoShigefumi IshiguroToshifumi WatanabeKazuto Uehara
    • Tomoyuki HamanoShigefumi IshiguroToshifumi WatanabeKazuto Uehara
    • G11C7/00
    • G11C8/04G11C11/41G11C2029/0411
    • According to one embodiment, a semiconductor memory device includes a memory array, an address counter, an address detecting circuit and a control circuit. The memory array has a plurality of memory cells arranged at crossing positions of word lines and bit lines. The address counter increments an address including a row address and a column address in synchronism with a clock to sequentially output the incremented addresses. The address detecting circuit detects an address previous to an address including a row address to which the row address is switched at the address output from the address counter to output a detection signal. The control circuit performs a precharging operation to the bit lines connected to the memory cells according to the detection signal output from the address detecting circuit.
    • 根据一个实施例,半导体存储器件包括存储器阵列,地址计数器,地址检测电路和控制电路。 存储器阵列具有布置在字线和位线的交叉位置处的多个存储单元。 地址计数器与时钟同步地增加包括行地址和列地址的地址,以顺序输出递增的地址。 地址检测电路在从地址计数器输出的地址处检测包括行地址切换到的行地址的地址,以输出检测信号。 控制电路根据从地址检测电路输出的检测信号对与存储单元连接的位线执行预充电操作。
    • 7. 发明授权
    • Optical module and manufacturing method therefor
    • 光模块及其制造方法
    • US07076135B2
    • 2006-07-11
    • US10666482
    • 2003-09-18
    • Koji YamadaTai TsuchizawaShingo UchiyamaTetsufumi ShojiJyun-ichi TakahashiToshifumi WatanabeEmi TamechikaHirofumi Morita
    • Koji YamadaTai TsuchizawaShingo UchiyamaTetsufumi ShojiJyun-ichi TakahashiToshifumi WatanabeEmi TamechikaHirofumi Morita
    • G02B6/26G02B6/42G02B6/10
    • G02B6/305G02B6/1228G02B2006/12176
    • An optical module includes an under cladding, a first core, a second core, and an over cladding. The under cladding has a flat shape as a whole. The first core has a quadrangular cross section and is placed on the under cladding. The second core is placed on a terminal end portion of the first core. The over cladding is placed in a region including the terminal end portion of the first core and the second core placed on the terminal end portion of the first core. The under cladding and the first core placed thereon constitute a first optical waveguide. The under cladding, the terminal end portion of the first core placed on the under cladding, the second core placed thereon, and the over cladding placed on and around the second core constitute a mode field size conversion portion. The under cladding, the second core placed on the under cladding, and the over cladding placed on and around the second core constitute a second optical waveguide. The first core is made of silicon. The first and second cores differ in cross-sectional shape. A manufacturing method for the optical module is also disclosed.
    • 光学模块包括下包层,第一芯,第二芯和外包层。 下包层整体呈扁平形状。 第一芯具有四边形横截面并且放置在下包层上。 第二芯放置在第一芯的末端部分上。 上包层放置在包括第一芯的末端部分和放置在第一芯的终端部分上的第二芯的区域中。 下敷层和放置在其上的第一芯构成第一光波导。 下包层,第一芯的终端部分放置在下包层上,第二芯放置在其上,并且放置在第二芯上和周围的上包层构成模场尺寸转换部分。 放置在下包层上的下包层,第二芯和放置在第二芯上并围绕第二芯的外包层构成第二光波导。 第一个核心由硅制成。 第一和第二芯的横截面形状不同。 还公开了一种用于光学模块的制造方法。
    • 10. 发明授权
    • Semiconductor memory device
    • 半导体存储器件
    • US08259523B2
    • 2012-09-04
    • US12836944
    • 2010-07-15
    • Toshifumi WatanabeTomoyuki HamanoShigefumi IshiguroKazuto Uehara
    • Toshifumi WatanabeTomoyuki HamanoShigefumi IshiguroKazuto Uehara
    • G11C7/00
    • G11C7/12G11C8/12G11C11/005
    • According to one embodiment, a semiconductor memory device includes a first memory, a second memory and a control circuit. The first memory includes a first bank number. The second memory includes a second bank number larger than the first bank number. The control circuit controls a precharge operation with respect to bit lines provided in the first and second memories. When performing, with respect to the first memory, a synchronous operation that is effected in synchronization with a clock, the control circuit changes over a second precharge operation to an operation time different from a first precharge operation during a period from the end of the initial first precharge operation to the start of the subsequent second precharge operation after receiving an address.
    • 根据一个实施例,半导体存储器件包括第一存储器,第二存储器和控制电路。 第一存储器包括第一个银行号码。 第二存储器包括大于第一存储体号的第二存储体号。 控制电路相对于设置在第一和第二存储器中的位线控制预充电操作。 当相对于第一存储器执行与时钟同步地进行的同步操作时,控制电路在初始化结束时间段内将第二预充电操作改变为与第一预充电操作不同的操作时间 在接收地址之后的第二预充电操作开始的第一预充电操作。