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1. 发明授权

US08207613B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08207613B2
公开(公告)日：2012-06-26
申请号：US12718374
申请日：2010-03-05
申请人： Yuki Okukawa , Satoru Takase
发明人： Yuki Okukawa , Satoru Takase
IPC分类号： H01L23/48
CPC分类号： H01L27/101 , H01L27/222 , H01L27/24
摘要： A semiconductor memory device includes a cell array layer including a first and a second wiring, which cross each other; a third wiring formed on a first wiring layer below the cell array layer; a fourth wiring formed on a second wiring layer above the cell array layer; and a contact extending in a stacking direction for connecting the third and the fourth wiring, wherein the device further comprises a redundant wiring layer being formed between the first and the second wiring layer, the redundant wiring layer being formed with a redundant wiring having a portion extending in the same direction as at least one of the third and the fourth wiring, and the third and the redundant wiring, and the fourth and the redundant wiring being connected by a plurality of contacts arranged along the portion extending in the same direction as the third or the fourth wiring.
摘要翻译：一种半导体存储器件，包括：一个包括彼此交叉的第一和第二布线的单元阵列层; 形成在所述电池阵列层下方的第一布线层上的第三布线; 形成在所述电池阵列层上方的第二布线层上的第四布线; 以及在堆叠方向上延伸的用于连接第三和第四布线的接触件，其中所述装置还包括在所述第一和第二布线层之间形成的冗余布线层，所述冗余布线层形成有冗余布线，所述冗余布线具有部分沿与第三和第四布线，第三布线和第三布线以及第三布线和第四布线中的至少一个相同的方向延伸，并且第四布线和冗余布线通过沿与沿着相同方向延伸的部分布置的多个触点连接第三或第四布线。

2. 发明授权

US08199557B2 Nonvolatile semiconductor memory device and method of resetting the same 有权
标题翻译：非易失性半导体存储器件及其复位方法
公开(公告)号：US08199557B2
公开(公告)日：2012-06-12
申请号：US12719528
申请日：2010-03-08
申请人： Hiroshi Maejima , Yuki Okukawa
发明人： Hiroshi Maejima , Yuki Okukawa
IPC分类号： G11C11/00
CPC分类号： G11C13/0002 , G11C13/0061
摘要： A nonvolatile semiconductor memory device includes: a plurality of memory cell arrays stacked on a semiconductor substrate and including a plurality of first wires, a plurality of second wires and memory cells disposed at intersections of the first wires and the second wires and having a rectifier element and a variable resistive element are connected in series; and a control circuit configured to selectively drive the first wires and the second wires. The control circuit executes a resetting operation to change a state of the variable resistive element from a low resistance state to a high resistance state. At a time of executing the resetting operation, the control circuit increases a pulse voltage to be applied to the variable resistive element to a first voltage, and then decreases the pulse voltage to a second voltage lower than the first voltage and higher than the ground voltage.
摘要翻译：非易失性半导体存储器件包括：多个存储单元阵列，堆叠在半导体衬底上并且包括多个第一布线，多个第二布线和存储单元，布置在第一布线和第二布线的交点处，并且具有整流元件和可变电阻元件串联连接; 以及控制电路，被配置为选择性地驱动第一线和第二线。控制电路执行将可变电阻元件的状态从低电阻状态改变为高电阻状态的复位操作。在执行复位操作时，控制电路将施加到可变电阻元件的脉冲电压增加到第一电压，然后将脉冲电压降低到低于第一电压并高于接地电压的第二电压。

3. 发明申请

US20090265591A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路设备
公开(公告)号：US20090265591A1
公开(公告)日：2009-10-22
申请号：US12415448
申请日：2009-03-31
申请人： Yuki Okukawa , Kazushige Kanda
发明人： Yuki Okukawa , Kazushige Kanda
IPC分类号： G11C29/04 , G06F11/22
CPC分类号： G01R31/3183 , G01R31/31919 , G11C16/04 , G11C29/028 , G11C29/48 , G11C29/50 , G11C29/56
摘要： A semiconductor integrated circuit device related to an embodiment of the present invention includes an address register which includes an internal selection circuit connected with a control circuit, a signal generation instruction circuit which instructs the control circuit so that a predetermined internal control signal is generated, a latch circuit, a plurality of which are arranged corresponding to a number of bits of test parameter data, the latch circuit latching test result data which is provided from the data program/read circuit and outputting the test result data to the selection circuit and externally, the control circuit generating an internal control signal which activates the selection circuit at a timing at which a fixed value data of the test parameter data is changed, and the selection circuit controlling a test so that a fixed value data of the test parameter data is changed.
摘要翻译：与本发明的实施例有关的半导体集成电路装置包括地址寄存器，其包括与控制电路连接的内部选择电路，指示控制电路以产生预定的内部控制信号的信号生成指令电路，锁存电路，其中多个对应于测试参数数据的位数排列，锁存电路锁存从数据程序/读取电路提供的测试结果数据，并将测试结果数据输出到选择电路和外部，所述控制电路产生内部控制信号，所述内部控制信号在所述测试参数数据的固定值数据被改变的定时激活所述选择电路，并且所述选择电路控制测试，使得所述测试参数数据的固定值数据被改变。

4. 发明授权

US08195993B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US08195993B2
公开(公告)日：2012-06-05
申请号：US13178982
申请日：2011-07-08
申请人： Yuki Okukawa , Kazushige Kanda
发明人： Yuki Okukawa , Kazushige Kanda
IPC分类号： G11C29/00
CPC分类号： G01R31/3183 , G01R31/31919 , G11C16/04 , G11C29/028 , G11C29/48 , G11C29/50 , G11C29/56
摘要： A semiconductor integrated circuit device related to an embodiment of the present invention includes an address register which includes an internal selection circuit connected with a control circuit, a signal generation instruction circuit which instructs the control circuit so that a predetermined internal control signal is generated, a latch circuit, a plurality of which are arranged corresponding to a number of bits of test parameter data, the latch circuit latching test result data which is provided from the data program/read circuit and outputting the test result data to the selection circuit and externally, the control circuit generating an internal control signal which activates the selection circuit at a timing at which a fixed value data of the test parameter data is changed, and the selection circuit controlling a test so that a fixed value data of the test parameter data is changed.
摘要翻译：与本发明的实施例有关的半导体集成电路装置包括地址寄存器，其包括与控制电路连接的内部选择电路，指示控制电路以产生预定的内部控制信号的信号生成指令电路，锁存电路，其中多个对应于测试参数数据的位数排列，锁存电路锁存从数据程序/读取电路提供的测试结果数据，并将测试结果数据输出到选择电路和外部，所述控制电路产生内部控制信号，所述内部控制信号在所述测试参数数据的固定值数据被改变的定时激活所述选择电路，并且所述选择电路控制测试，使得所述测试参数数据的固定值数据被改变。

5. 发明授权

US08006145B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US08006145B2
公开(公告)日：2011-08-23
申请号：US12415448
申请日：2009-03-31
申请人： Yuki Okukawa , Kazushige Kanda
发明人： Yuki Okukawa , Kazushige Kanda
IPC分类号： G11C29/00
CPC分类号： G01R31/3183 , G01R31/31919 , G11C16/04 , G11C29/028 , G11C29/48 , G11C29/50 , G11C29/56
摘要： A semiconductor integrated circuit device related to an embodiment of the present invention includes an address register which includes an internal selection circuit connected with a control circuit, a signal generation instruction circuit which instructs the control circuit so that a predetermined internal control signal is generated, a latch circuit, a plurality of which are arranged corresponding to a number of bits of test parameter data, the latch circuit latching test result data which is provided from the data program/read circuit and outputting the test result data to the selection circuit and externally, the control circuit generating an internal control signal which activates the selection circuit at a timing at which a fixed value data of the test parameter data is changed, and the selection circuit controlling a test so that a fixed value data of the test parameter data is changed.
摘要翻译：与本发明的实施例有关的半导体集成电路装置包括地址寄存器，其包括与控制电路连接的内部选择电路，指示控制电路以产生预定的内部控制信号的信号生成指令电路，锁存电路，其中多个对应于测试参数数据的位数排列，锁存电路锁存从数据程序/读取电路提供的测试结果数据，并将测试结果数据输出到选择电路和外部，所述控制电路产生内部控制信号，所述内部控制信号在所述测试参数数据的固定值数据被改变的定时激活所述选择电路，并且所述选择电路控制测试，使得所述测试参数数据的固定值数据被改变。

6. 发明授权

US08537598B2 Nonvolatile semiconductor memory device and method for resetting the same 有权
标题翻译：非易失性半导体存储器件及其复位方法
公开(公告)号：US08537598B2
公开(公告)日：2013-09-17
申请号：US13475349
申请日：2012-05-18
申请人： Hiroshi Maejima , Yuki Okukawa
发明人： Hiroshi Maejima , Yuki Okukawa
IPC分类号： G11C11/00
CPC分类号： G11C13/0002 , G11C13/0061
摘要： A nonvolatile semiconductor memory device includes: a plurality of memory cell arrays stacked on a semiconductor substrate and including a plurality of first wires, a plurality of second wires and memory cells disposed at intersections of the first wires and the second wires and having a rectifier element and a variable resistive element are connected in series; and a control circuit configured to selectively drive the first wires and the second wires. The control circuit executes a resetting operation to change a state of the variable resistive element from a low resistance state to a high resistance state. At a time of executing the resetting operation, the control circuit increases a pulse voltage to be applied to the variable resistive element to a first voltage, and then decreases the pulse voltage to a second voltage lower than the first voltage and higher than the ground voltage.
摘要翻译：非易失性半导体存储器件包括：多个存储单元阵列，堆叠在半导体衬底上并且包括多个第一布线，多个第二布线和存储单元，布置在第一布线和第二布线的交点处，并且具有整流元件和可变电阻元件串联连接; 以及控制电路，被配置为选择性地驱动第一线和第二线。控制电路执行将可变电阻元件的状态从低电阻状态改变为高电阻状态的复位操作。在执行复位操作时，控制电路将施加到可变电阻元件的脉冲电压增加到第一电压，然后将脉冲电压降低到低于第一电压并高于接地电压的第二电压。

7. 发明申请

US20120230082A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF RESETTING THE SAME 有权
标题翻译：非易失性半导体存储器件及其复位方法
公开(公告)号：US20120230082A1
公开(公告)日：2012-09-13
申请号：US13475349
申请日：2012-05-18
申请人： Hiroshi MAEJIMA , Yuki Okukawa
发明人： Hiroshi MAEJIMA , Yuki Okukawa
IPC分类号： G11C11/00
CPC分类号： G11C13/0002 , G11C13/0061
摘要： A nonvolatile semiconductor memory device includes: a plurality of memory cell arrays stacked on a semiconductor substrate and including a plurality of first wires, a plurality of second wires and memory cells disposed at intersections of the first wires and the second wires and having a rectifier element and a variable resistive element are connected in series; and a control circuit configured to selectively drive the first wires and the second wires. The control circuit executes a resetting operation to change a state of the variable resistive element from a low resistance state to a high resistance state. At a time of executing the resetting operation, the control circuit increases a pulse voltage to be applied to the variable resistive element to a first voltage, and then decreases the pulse voltage to a second voltage lower than the first voltage and higher than the ground voltage.
摘要翻译：非易失性半导体存储器件包括：多个存储单元阵列，堆叠在半导体衬底上并且包括多个第一布线，多个第二布线和存储单元，布置在第一布线和第二布线的交点处，并且具有整流元件和可变电阻元件串联连接; 以及控制电路，被配置为选择性地驱动第一线和第二线。控制电路执行将可变电阻元件的状态从低电阻状态改变为高电阻状态的复位操作。在执行复位操作时，控制电路将施加到可变电阻元件的脉冲电压增加到第一电压，然后将脉冲电压降低到低于第一电压并高于接地电压的第二电压。

8. 发明申请

US20100232207A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF RESETTING THE SAME 有权
标题翻译：非易失性半导体存储器件及其复位方法
公开(公告)号：US20100232207A1
公开(公告)日：2010-09-16
申请号：US12719528
申请日：2010-03-08
申请人： Hiroshi MAEJIMA , Yuki Okukawa
发明人： Hiroshi MAEJIMA , Yuki Okukawa
IPC分类号： G11C11/00 , G11C5/14
CPC分类号： G11C13/0002 , G11C13/0061
摘要： A nonvolatile semiconductor memory device includes: a plurality of memory cell arrays stacked on a semiconductor substrate and including a plurality of first wires, a plurality of second wires and memory cells disposed at intersections of the first wires and the second wires and having a rectifier element and a variable resistive element are connected in series; and a control circuit configured to selectively drive the first wires and the second wires. The control circuit executes a resetting operation to change a state of the variable resistive element from a low resistance state to a high resistance state. At a time of executing the resetting operation, the control circuit increases a pulse voltage to be applied to the variable resistive element to a first voltage, and then decreases the pulse voltage to a second voltage lower than the first voltage and higher than the ground voltage.
摘要翻译：非易失性半导体存储器件包括：多个存储单元阵列，堆叠在半导体衬底上并且包括多个第一布线，多个第二布线和存储单元，布置在第一布线和第二布线的交点处，并且具有整流元件和可变电阻元件串联连接; 以及控制电路，被配置为选择性地驱动第一线和第二线。控制电路执行将可变电阻元件的状态从低电阻状态改变为高电阻状态的复位操作。在执行复位操作时，控制电路将施加到可变电阻元件的脉冲电压增加到第一电压，然后将脉冲电压降低到低于第一电压并高于接地电压的第二电压。

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