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    • 1. 发明授权
    • Semiconductor data processor
    • 半导体数据处理器
    • US07356649B2
    • 2008-04-08
    • US10520653
    • 2002-09-30
    • Yuki KondohTatsuya KameiMakoto Ishikawa
    • Yuki KondohTatsuya KameiMakoto Ishikawa
    • G06F12/00
    • G06F12/0888
    • A semiconductor data processor has a first memory(6) constituting a cache memory, a second memory(20) capable of being a cacheable area or a non-cacheable area by the first memory, and a read buffer(12) capable of carrying out an operation for outputting data corresponding to a read access when the second memory is read accessed as the non-cacheable area. The designation of the cacheable area and the non-cacheable area for the second memory is determined by the designation of a cacheable area or a non-cacheable area for a memory space to which the second memory is mapped. The designation may be carried out in the operation mode of the data processor or by setting a control register, for example.
    • 半导体数据处理器具有构成高速缓冲存储器的第一存储器(6),能够由第一存储器构成可高速缓存区域或不可缓存区域的第二存储器(20),以及能够执行 当第二存储器被读取访问作为不可缓存区域时,用于输出与读访问相对应的数据的操作。 用于第二存储器的可缓存区域和不可缓存区域的指定由第二存储器映射到的存储器空间的可缓存区域或不可缓存区域的指定来确定。 该指定可以在数据处理器的操作模式下执行,或者例如设置控制寄存器。
    • 2. 发明申请
    • Semiconductor data processor
    • 半导体数据处理器
    • US20050257011A1
    • 2005-11-17
    • US10520653
    • 2002-09-30
    • Yuki KondohTatsuya KameiMakoto Ishikawa
    • Yuki KondohTatsuya KameiMakoto Ishikawa
    • G06F12/08G06F12/00
    • G06F12/0888
    • A semiconductor data processor has a first memory(6) constituting a cache memory, a second memory(20) capable of being a cacheable area or a non-cacheable area by the first memory, and a read buffer(12) capable of carrying out an operation for outputting data corresponding to a read access when the second memory is read accessed as the non-cacheable area. The designation of the cacheable area and the non-cacheable area for the second memory is determined by the designation of a cacheable area or a non-cacheable area for a memory space to which the second memory is mapped. The designation may be carried out in the operation mode of the data processor or by setting a control register, for example.
    • 半导体数据处理器具有构成高速缓冲存储器的第一存储器(6),能够由第一存储器构成可高速缓存区域或不可缓存区域的第二存储器(20),以及能够执行 当第二存储器被读取访问作为不可缓存区域时,用于输出与读访问相对应的数据的操作。 用于第二存储器的可缓存区域和不可缓存区域的指定由第二存储器映射到的存储器空间的可缓存区域或不可缓存区域的指定来确定。 该指定可以在数据处理器的操作模式下执行,或者例如设置控制寄存器。
    • 3. 发明申请
    • DATA PROCESSOR
    • 数据处理器
    • US20110107064A1
    • 2011-05-05
    • US12915158
    • 2010-10-29
    • Hiroaki NAKAYAYuki KondohMakoto Ishikawa
    • Hiroaki NAKAYAYuki KondohMakoto Ishikawa
    • G06F9/30
    • G06F9/382G06F9/30149G06F9/3017G06F9/30185G06F9/3802G06F9/3822
    • The present invention realizes an efficient superscalar instruction issue and low power consumption at an instruction set including instructions with prefixes. An instruction fetch unit is adopted which determines whether an instruction code is of a prefix code or an instruction code other than it, and outputs the result of determination and the 16-bit instruction code. Along with it, decoders each of which decodes the instruction code, based on the result of determination, and decoders each of which decodes the prefix code, are disposed separately. Further, a prefix is supplied to each decoder prior to a fixed-length instruction code like 16 bits modified with it. A fixed-length instruction code following the prefix code is supplied to each decoder of the same pipeline as the decoder for the prefix code.
    • 本发明在包括具有前缀的指令的指令集上实现有效的超标量指令问题和低功耗。 采用指令取出单元,其判定指令码是否是前缀码,也可以是除了指令码以外的指令码,并输出确定结果和16位指令码。 与此同时,基于确定结果解码指令代码的解码器和分别解码前缀码的解码器分别设置。 此外,在固定长度指令代码(如16位修改)之前,将前缀提供给每个解码器。 与前缀码相邻的固定长度指令代码被提供给与前缀码的解码器相同的流水线的每个解码器。
    • 4. 发明授权
    • Semiconductor device with instruction code and prefix code predecoders
    • 具有指令码和前缀码预解码器的半导体器件
    • US08924689B2
    • 2014-12-30
    • US12915158
    • 2010-10-29
    • Hiroaki NakayaYuki KondohMakoto Ishikawa
    • Hiroaki NakayaYuki KondohMakoto Ishikawa
    • G06F9/30G06F9/38
    • G06F9/382G06F9/30149G06F9/3017G06F9/30185G06F9/3802G06F9/3822
    • The present invention realizes an efficient superscalar instruction issue and low power consumption at an instruction set including instructions with prefixes. An instruction fetch unit is adopted which determines whether an instruction code is of a prefix code or an instruction code other than it, and outputs the result of determination and the 16-bit instruction code. Along with it, decoders each of which decodes the instruction code, based on the result of determination, and decoders each of which decodes the prefix code, are disposed separately. Further, a prefix is supplied to each decoder prior to a fixed-length instruction code like 16 bits modified with it. A fixed-length instruction code following the prefix code is supplied to each decoder of the same pipeline as the decoder for the prefix code.
    • 本发明在包括具有前缀的指令的指令集上实现有效的超标量指令问题和低功耗。 采用指令取出单元,其判定指令码是否是前缀码,也可以是除了指令码以外的指令码,并输出确定结果和16位指令码。 与此同时,基于确定结果解码指令代码的解码器和分别解码前缀码的解码器分别设置。 此外,在固定长度指令代码(如16位修改)之前,将前缀提供给每个解码器。 与前缀码相邻的固定长度指令代码被提供给与前缀码的解码器相同的流水线的每个解码器。
    • 5. 发明申请
    • Data processing device
    • 数据处理装置
    • US20060143405A1
    • 2006-06-29
    • US11315320
    • 2005-12-23
    • Makoto IshikawaTatsuya Kamei
    • Makoto IshikawaTatsuya Kamei
    • G06F13/28
    • G06F12/1045G06F12/0855G06F12/0859G06F12/1054Y02D10/13
    • A data processor has a central processing unit and a plurality of logical blocks (1104) to be connected to the central processing unit, and the central processing unit sets a predetermined logical block to be a control object based on a result of decode of a predetermined instruction code (CBP) and a function of the predetermined logical block is selected based on the result of decode of the predetermined instruction code and a part of address information which is incidental to the predetermined instruction code (TAG [14:13]). It is possible to decide an operating object in an early stage before reaching a memory access stage of a pipeline without requiring to allocate the instruction code in a one-to-one correspondence for the operation of the predetermined logical block. Consequently, it is possible to suppress a consumption of the instruction code, a useless power consumption and a reduction in a processing performance of an operation for a specific logical block, for example, a cache coherency operation or a TLB page attribute operation in the same operation.
    • 数据处理器具有中央处理单元和要连接到中央处理单元的多个逻辑块(1104),并且中央处理单元基于预定的解码的结果将预定逻辑块设置为控制对象 基于预定指令代码的解码结果和与预定指令代码相关的部分地址信息(TAG [14:13])来选择指令代码(CBP)和预定逻辑块的功能。 可以在达到流水线的存储器访问级之前的早期阶段决定一个操作对象,而不需要以一一对应的方式分配指令代码,用于预定逻辑块的操作。 因此,可以抑制指令码的消耗,无用的功率消耗和用于特定逻辑块的操作的处理性能的降低,例如高速缓存一致性操作或其中的TLB页面属性操作 操作。