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1. 发明授权

US08887030B2 Encoder and encoding method providing incremental redundancy 有权
标题翻译：编码和编码方法提供增量冗余
公开(公告)号：US08887030B2
公开(公告)日：2014-11-11
申请号：US13579735
申请日：2011-02-18
申请人： Nabil Loghin , Lothar Stadelmeier , Joerg Robert , Samuel Asangbeng Atungsiri , Makiko Yamamoto , Yuji Shinohara , Lui Sakai , Takashi Yokokawa
发明人： Nabil Loghin , Lothar Stadelmeier , Joerg Robert , Samuel Asangbeng Atungsiri , Makiko Yamamoto , Yuji Shinohara , Lui Sakai , Takashi Yokokawa
IPC分类号： H03M13/00 , H04L1/00 , H03M13/37 , H03M13/11
CPC分类号： H03M13/11 , H03M13/1165 , H03M13/3761 , H03M13/6519 , H04L1/0036 , H04L1/0045 , H04L1/0057 , H04L1/0059 , H04L1/0068 , H04L1/0083 , H04L2001/0098
摘要： The present invention relates to an encoder for error correction code encoding input data words (D) into codewords (Z1, Z2), comprising: an encoder input (1451) for receiving input data words (D) each comprising a first number Kldpc of information symbols, an encoding means (1452) for encoding an input data word (D) into a codeword (Z1, Z2, Z3, Z4) such that a codeword comprises a basic codeword portion (B) including a data portion (D) and a basic parity portion (Pb) of a second number Nldpc−Kldpc of basic parity symbols, and an auxiliary codeword portion (A) including an auxiliary parity portion (Pa) of a third number MIR of auxiliary parity symbols, wherein said encoding means (14) is adapted i) for generating said basic codeword portion (B) from an input data word (D) according to a first code, wherein a basic parity symbol is generated by accumulating an information symbol at a parity symbol address determined according to a first address generation rule, and ii) for generating said auxiliary codeword portion (A) from an input data word (D) according to a second code, wherein an auxiliary parity symbol is generated by accumulating an information symbol m at a parity symbol address γ, wherein said parity symbol addresses γ are determined according to a second address generation rule Nldpc−Kldpc+{x+m mod Ga×QIR} mod MIR if x>Nldpc−Kldpc, wherein x denotes the addresses of a parity symbol accumulator corresponding to the first information symbol of a group of size Ga and QIR is an auxiliary code rate dependent, predefined constant, and an encoder output (1454) for outputting said codewords (Z1, Z2).
摘要翻译：本发明涉及一种用于将输入数据字（D）编码成码字（Z1，Z2）的纠错码的编码器，包括：编码器输入端（1451），用于接收输入数据字（D），每个输入数据字包括第一数字信号Kldpc 符号，用于将输入数据字（D）编码为码字（Z1，Z2，Z3，Z4）的编码装置（1452），使得码字包括基本码字部分（B），其包括数据部分（D）和基本奇偶校验符号的第二编号Nldpc-Kldpc的基本奇偶校验部分（Pb）和包括辅助奇偶校验符号的第三数量MIR的辅助奇偶校验部分（Pa）的辅助码字部分（A），其中所述编码装置）适于i）用于根据第一代码从输入数据字（D）产生所述基本码字部分（B），其中通过在根据第一代码确定的奇偶校验符号地址处累积信息符号来生成基本奇偶校验符号地址生成规则，和ii）生成s 根据第二代码从输入数据字（D）辅助辅助码字部分（A），其中通过在奇偶校验符号地址γ处累积信息符号m来生成辅助奇偶校验符号，其中所述奇偶校验符号地址γ根据如果x> Nldpc-Kldpc，则到第二地址生成规则Nldpc-Kldpc + {x + m mod Ga×QIR} mod MIR，其中x表示对应于大小为Ga的组的第一信息符号的奇偶校验符号累加器的地址， QIR是辅助代码速率相关的预定义常数，以及用于输出所述码字（Z1，Z2）的编码器输出（1454）。

2. 发明申请

US20120320994A1 ENCODER AND ENCODING METHOD PROVIDING INCREMENTAL REDUNDANCY 有权
标题翻译：编码和编码方法提供增值冗余
公开(公告)号：US20120320994A1
公开(公告)日：2012-12-20
申请号：US13579735
申请日：2011-02-18
申请人： Nabil Loghin , Lothar Stadelmeier , Joerg Robert , Samuel Asangbeng Atungsiri , Makiko Yamamoto , Yuji Shinohara , Lui Sakai , Takashi Yokokawa
发明人： Nabil Loghin , Lothar Stadelmeier , Joerg Robert , Samuel Asangbeng Atungsiri , Makiko Yamamoto , Yuji Shinohara , Lui Sakai , Takashi Yokokawa
IPC分类号： H04N7/56
CPC分类号： H03M13/11 , H03M13/1165 , H03M13/3761 , H03M13/6519 , H04L1/0036 , H04L1/0045 , H04L1/0057 , H04L1/0059 , H04L1/0068 , H04L1/0083 , H04L2001/0098
摘要： The present invention relates to an encoder for error correction code encoding input data words (D) into codewords (Z1, Z2), comprising: an encoder input (1451) for receiving input data words (D) each comprising a first number Kldpc of information symbols, an encoding means (1452) for encoding an input data word (D) into a codeword (Z1, Z2, Z3, Z4) such that a codeword comprises a basic codeword portion (B) including a data portion (D) and a basic parity portion (Pb) of a second number Nldpc−Kldpc of basic parity symbols, and an auxiliary codeword portion (A) including an auxiliary parity portion (Pa) of a third number MIR of auxiliary parity symbols, wherein said encoding means (14) is adapted i) for generating said basic codeword portion (B) from an input data word (D) according to a first code, wherein a basic parity symbol is generated by accumulating an information symbol at a parity symbol address determined according to a first address generation rule, and ii) for generating said auxiliary codeword portion (A) from an input data word (D) according to a second code, wherein an auxiliary parity symbol is generated by accumulating an information symbol m at a parity symbol address γ, wherein said parity symbol addresses γ are determined according to a second address generation rule Nldpc−Kldpc+{x+m mod Ga×QIR} mod MIR if x>Nldpc−Kldpc, wherein x denotes the addresses of a parity symbol accumulator corresponding to the first information symbol of a group of size Ga and QIR is an auxiliary code rate dependent, predefined constant, and an encoder output (1454) for outputting said codewords (Z1, Z2).
摘要翻译：本发明涉及一种用于将输入数据字（D）编码成码字（Z1，Z2）的纠错码的编码器，包括：编码器输入端（1451），用于接收输入数据字（D），每个输入数据字包括第一数字信号Kldpc 符号，用于将输入数据字（D）编码为码字（Z1，Z2，Z3，Z4）的编码装置（1452），使得码字包括基本码字部分（B），其包括数据部分（D）和基本奇偶校验符号的第二编号Nldpc-Kldpc的基本奇偶校验部分（Pb）和包括辅助奇偶校验符号的第三数量MIR的辅助奇偶校验部分（Pa）的辅助码字部分（A），其中所述编码装置）适于i）用于根据第一代码从输入数据字（D）产生所述基本码字部分（B），其中通过在根据第一代码确定的奇偶校验符号地址处累积信息符号来生成基本奇偶校验符号地址生成规则，和ii）生成s 根据第二代码从输入数据字（D）辅助辅助码字部分（A），其中通过在奇偶校验符号地址γ处累积信息符号m来生成辅助奇偶校验符号，其中所述奇偶校验符号地址γ根据如果x> Nldpc-Kldpc，则到第二地址生成规则Nldpc-Kldpc + {x + m mod Ga×QIR} mod MIR，其中x表示对应于大小为Ga的组的第一信息符号的奇偶校验符号累加器的地址， QIR是辅助代码速率相关的预定义常数，以及用于输出所述码字（Z1，Z2）的编码器输出（1454）。

3. 发明授权

US09106256B2 Data processing device and data processing method for encoding/decoding information bits 有权
标题翻译：用于对信息位进行编码/解码的数据处理装置和数据处理方法
公开(公告)号：US09106256B2
公开(公告)日：2015-08-11
申请号：US13818709
申请日：2011-08-25
申请人： Yuji Shinohara , Atsushi Kikuchi , Makiko Yamamoto , Takashi Yokokawa
发明人： Yuji Shinohara , Atsushi Kikuchi , Makiko Yamamoto , Takashi Yokokawa
IPC分类号： H03M13/00 , H03M13/05 , H03M13/03 , H03M13/11 , H03M13/25 , H03M13/27 , H03M13/29 , H03M13/35 , H04L27/36 , H03M13/15
CPC分类号： H03M13/05 , H03M13/036 , H03M13/1165 , H03M13/152 , H03M13/255 , H03M13/2707 , H03M13/271 , H03M13/2906 , H03M13/356 , H03M13/6552 , H04L27/36
摘要： A data processing device and a data processing method capable of improving the resistance to error of data. An LDPC encoder performs encoding using an LDPC code having a code length of 4320 bits and a coded rate of one of four types including ½, 7/12, ⅔, ¾. A parity check matrix H of the LDPC code is configured by arranging elements of 1's of an information matrix, which are determined based on a parity check matrix initial value table of the parity check matrix H representing positions of elements of 1's of the information matrix corresponding to an information length according to the code length and the coded rate for every 72 columns, in a column direction at a period of 72 columns. The parity check matrix initial value table, for example, is used for digital broadcasting for mobile terminals.
摘要翻译：一种数据处理装置和数据处理方法，能够提高数据的误差抵抗能力。 LDPC编码器使用码长为4320位的LDPC码和包括½，7/12，⅔，¾的四种类型之一的编码速率来执行编码。通过布置基于奇偶校验矩阵H的奇偶校验矩阵初始值表确定的信息矩阵的1的元素来表示LDPC码的奇偶校验矩阵H，该奇偶校验矩阵初始值表示对应于信息矩阵的1的元素的位置根据每72列的码长和编码速率在72列的列方向上的信息长度。奇偶校验矩阵初始值表例如用于移动终端的数字广播。

4. 发明授权

US09094043B2 Data processing device and data processing method 有权
标题翻译：数据处理装置和数据处理方法
公开(公告)号：US09094043B2
公开(公告)日：2015-07-28
申请号：US13982494
申请日：2012-02-01
申请人： Yuji Shinohara , Makiko Yamamoto , Takashi Yokokawa
发明人： Yuji Shinohara , Makiko Yamamoto , Takashi Yokokawa
IPC分类号： H03M13/00 , H03M13/09 , H03M13/03 , H03M13/11 , H03M13/25 , H03M13/27 , H03M13/29 , H04L1/00 , H03M13/15 , H04L27/26
CPC分类号： H03M13/09 , H03M13/036 , H03M13/1165 , H03M13/152 , H03M13/255 , H03M13/2707 , H03M13/271 , H03M13/2906 , H04L1/0045 , H04L1/0057 , H04L1/0065 , H04L1/0072 , H04L27/2626 , H04L27/2647
摘要： A data processing device and a data processing method capable of improving resistance to errors. Code bits of an LDPC code with a code length N of 16200 bits is written to, for example, eight storage units. When the code bits are stored in the storage units, a process of changing the storage start position of the code bits for each storage unit is performed as a sorting process of sorting the bits of the LDPC code such that a plurality of code bits corresponding to 1s in an arbitrary row of the parity check matrix of the LDPC code are not included in a single symbol which is read from the storage units. The present technology can be applied to, for example, the transmission of the LDPC code.
摘要翻译：一种数据处理装置和能够改善抵抗误差的数据处理方法。具有16200比特的码长N的LDPC码的码比特被写入例如八个存储单元。当代码位被存储在存储单元中时，执行改变每个存储单元的代码位的存储开始位置的处理，作为对LDPC码的比特进行排序的排序处理，使得与 LDPC码的奇偶校验矩阵的任意行中的1个不包含在从存储单元读取的单个符号中。本技术可以应用于例如LDPC码的传输。

5. 发明申请

US20130311850A1 DATA PROCESSING DEVICE AND DATA PROCESSING METHOD 有权
标题翻译：数据处理设备和数据处理方法
公开(公告)号：US20130311850A1
公开(公告)日：2013-11-21
申请号：US13982494
申请日：2012-02-01
申请人： Yuji Shinohara , Makiko Yamamoto , Takashi Yokokawa
发明人： Yuji Shinohara , Makiko Yamamoto , Takashi Yokokawa
IPC分类号： H03M13/09
CPC分类号： H03M13/09 , H03M13/036 , H03M13/1165 , H03M13/152 , H03M13/255 , H03M13/2707 , H03M13/271 , H03M13/2906 , H04L1/0045 , H04L1/0057 , H04L1/0065 , H04L1/0072 , H04L27/2626 , H04L27/2647
摘要： A data processing device and a data processing method capable of improving resistance to errors. Code bits of an LDPC code with a code length N of 16200 bits is written to, for example, eight storage units. When the code bits are stored in the storage units, a process of changing the storage start position of the code bits for each storage unit is performed as a sorting process of sorting the bits of the LDPC code such that a plurality of code bits corresponding to 1s in an arbitrary row of the parity check matrix of the LDPC code are not included in a single symbol which is read from the storage units. The present technology can be applied to, for example, the transmission of the LDPC code.
摘要翻译：一种数据处理装置和能够改善抵抗误差的数据处理方法。具有16200比特的码长N的LDPC码的码比特被写入例如八个存储单元。当代码位被存储在存储单元中时，执行改变每个存储单元的代码位的存储开始位置的处理，作为对LDPC码的比特进行排序的排序处理，使得与 LDPC码的奇偶校验矩阵的任意行中的1个不包含在从存储单元读取的单个符号中。本技术可以应用于例如LDPC码的传输。

6. 发明申请

US20130254617A1 DATA PROCESSING DEVICE AND DATA PROCESSING METHOD 有权
标题翻译：数据处理设备和数据处理方法
公开(公告)号：US20130254617A1
公开(公告)日：2013-09-26
申请号：US13818709
申请日：2011-08-25
申请人： Yuji Shinohara , Atsushi Kikuchi , Makiko Yamamoto , Takashi Yokokawa
发明人： Yuji Shinohara , Atsushi Kikuchi , Makiko Yamamoto , Takashi Yokokawa
IPC分类号： H03M13/05
CPC分类号： H03M13/05 , H03M13/036 , H03M13/1165 , H03M13/152 , H03M13/255 , H03M13/2707 , H03M13/271 , H03M13/2906 , H03M13/356 , H03M13/6552 , H04L27/36
摘要： The present invention relates to a data processing device and a data processing method capable of improving the resistance to error of data. An LDPC encoder 115 performs encoding using an LDPC code having a code length of 4320 bits and a coded rate of one of four types including ½, 7/12, ⅔, ¾. A parity check matrix H of the LDPC code is configured by arranging elements of 1's of an information matrix, which are determined based on a parity check matrix initial value table of the parity check matrix H representing positions of elements of 1's of the information matrix corresponding to an information length according to the code length and the coded rate for every 72 columns, in a column direction at a period of 72 columns. The parity check matrix initial value table, for example, is used for digital broadcasting for mobile terminals. The present invention can be applied in a case where LDPC encoding is performed.
摘要翻译：本发明涉及能够提高数据的误差抵抗的数据处理装置和数据处理方法。 LDPC编码器115使用码长为4320位的LDPC码和包括½，7 / 12,2 / 3，¾的四种类型中的一种的编码速率进行编码。通过布置基于奇偶校验矩阵H的奇偶校验矩阵初始值表确定的信息矩阵的1的元素来表示LDPC码的奇偶校验矩阵H，该奇偶校验矩阵初始值表示对应于信息矩阵的1的元素的位置根据每72列的码长和编码速率在72列的列方向上的信息长度。奇偶校验矩阵初始值表例如用于移动终端的数字广播。本发明可以应用于执行LDPC编码的情况。

7. 发明授权

US09135108B2 Data processing device and data processing method 有权
标题翻译：数据处理装置和数据处理方法
公开(公告)号：US09135108B2
公开(公告)日：2015-09-15
申请号：US14116231
申请日：2012-06-08
申请人： Yuji Shinohara , Makiko Yamamoto
发明人： Yuji Shinohara , Makiko Yamamoto
IPC分类号： G06F11/10 , H03M13/03 , H03M13/11 , H03M13/25 , H03M13/27 , H03M13/29 , H03M13/15 , H04L1/00 , H04L27/36 , H04L27/38 , H03M13/35 , H03M13/00
CPC分类号： G06F11/10 , H03M13/036 , H03M13/1165 , H03M13/1168 , H03M13/152 , H03M13/255 , H03M13/271 , H03M13/2906 , H03M13/2945 , H03M13/356 , H03M13/6552 , H04L1/0047 , H04L1/0057 , H04L27/36 , H04L27/38
摘要： The present technique relates to a data processing device and a data processing method that enable resistance to error of data to be improved.In the case in which an LDPC code having a code length of 16200 bits and an encoding rate of 8/15 is mapped to 16 signal points, if (#i+1)-th bits from most significant bits of sign bits of 4×2 bits and symbol bits of 4×2 bits of two consecutive symbols are set to bits b#i and y#i, respectively, a demultiplexer performs interchanging to allocate b0, b1, b2, b3, b4, b5, b6, and b7 to y0, y4, y3, y1, y2, y5, y6, and y7, respectively. The present technique can be applied to a transmission system or the like transmitting an LDPC code.
摘要翻译：本技术涉及能够提高数据的误差抵抗的数据处理装置和数据处理方法。在码长为16200比特，编码速率为8/15的LDPC码被映射到16个信号点的情况下，如果符号位的最高有效位为4×（＃i + 1） 2位和两个连续符号的4×2位的符号位分别被设置为位b＃i和y＃i，解复用器执行交换以分配b0，b1，b2，b3，b4，b5，b6和b7 分别为y0，y4，y3，y1，y2，y5，y6和y7。本技术可以应用于发送LDPC码的传输系统等。

8. 发明授权

US09106263B2 Data processing device and data processing method 有权
标题翻译：数据处理装置和数据处理方法
公开(公告)号：US09106263B2
公开(公告)日：2015-08-11
申请号：US13883118
申请日：2011-11-29
申请人： Makiko Yamamoto , Yuji Shinohara
发明人： Makiko Yamamoto , Yuji Shinohara
IPC分类号： H03M13/00 , H03M13/13 , H03M13/03 , H03M13/11 , H03M13/25 , H03M13/27 , H03M13/29 , H03M13/35 , H03M13/15
CPC分类号： H03M13/13 , H03M13/033 , H03M13/1165 , H03M13/152 , H03M13/255 , H03M13/2707 , H03M13/2906 , H03M13/356
摘要： Data processing devices and data process methods that can increase tolerance for data errors. An LDPC encoder performs encoding with an LDPC code having the code length of 16200 bits and one of the six code rates of 1/5, 1/3, 2/5, 4/9, 3/5, and 2/3. The parity check matrix H of the LDPC code is formed by arranging the elements “1” of an information matrix in the column direction in 360-column cycles, the information matrix corresponding to the information length of the parity check matrix H, the information length corresponding to the code length and the code rate, the information matrix being defined by a check matrix initial value table that shows the positions of the elements “1” of the information matrix at intervals of 360 columns. The check matrix initial value table is designed for digital broadcasting intended for portable terminals, for example. The present invention can be applied to cases where LDPC encoding and LDPC decoding are performed.
摘要翻译：可以增加数据错误容限的数据处理设备和数据处理方法。 LDPC编码器使用码长为16200比特和六分之一码率为1/5，1/3，2 / 5,4 / 9,3 / 5和2/3的LDPC码执行编码。 LDPC码的奇偶校验矩阵H通过在列方向上以360列循环布置信息矩阵的元素“1”，形成与奇偶校验矩阵H的信息长度对应的信息矩阵，信息长度对应于代码长度和码率，信息矩阵由以360列的间隔显示信息矩阵的元素“1”的位置的校验矩阵初始值表定义。检查矩阵初始值表例如被设计用于便携式终端的数字广播。本发明可以应用于执行LDPC编码和LDPC解码的情况。

9. 发明授权

US09071276B2 Data-processing device and data-processing method 有权
标题翻译：数据处理设备和数据处理方法
公开(公告)号：US09071276B2
公开(公告)日：2015-06-30
申请号：US13997695
申请日：2012-01-12
申请人： Yuji Shinohara , Makiko Yamamoto
发明人： Yuji Shinohara , Makiko Yamamoto
IPC分类号： H03M13/00 , H03M13/13 , H04L1/00 , H03M13/03 , H03M13/11 , H03M13/25 , H03M13/27 , H03M13/29 , H03M13/35 , H03M13/15 , H04L27/34
CPC分类号： H03M13/13 , H03M13/036 , H03M13/1165 , H03M13/152 , H03M13/255 , H03M13/2707 , H03M13/271 , H03M13/2906 , H03M13/356 , H03M13/6552 , H04L1/0041 , H04L1/0045 , H04L1/0057 , H04L1/0058 , H04L27/34
摘要： The present technology relates to a data-processing device and a data-processing method, which are capable of improving tolerance for an error of data.When an LDPC code having a code length of 16200 bits is mapped to 16 signal points, a demultiplexer performs exchanging such that when a (#i+1)-th bit from a most significant bit of code bits of 4×2 bits and a (#i+1)-th bit from a most significant bit of symbol bits of 4×2 bits of 2 consecutive symbols are represented by a bit b#i and a bit y#i, respectively, for LDPC codes having coding rates of 1/5, 4/15, and 1/3, b0 is allocated to y4, b1 is allocated to y3, b2 is allocated to y2, b3 is allocated to y1, b4 is allocated to y6, b5 is allocated to y5, b6 is allocated to y7, and b7 is allocated to y0. For example, the present invention can be applied to a transmission system that transmits an LDPC code or the like.
摘要翻译：本技术涉及能够提高数据误差容限的数据处理装置和数据处理方法。当具有16200比特的码长的LDPC码被映射到16个信号点时，解复用器进行交换，使得当从4×2比特的码比特的最高有效比特和第（i + 1）比特的第对于具有编码率的LDPC码，分别由位b＃i和位y＃i表示来自2个连续符号的4×2位的最高有效位的第（i + 1）比特 1/5,4 / 15和1/3，b0分配给y4，b1分配给y3，b2分配给y2，b3分配给y1，b4分配给y6，b5分配给y5，b6 分配给y7，b7分配给y0。例如，本发明可以应用于发送LDPC码等的发送系统。

10. 发明申请

US20130166992A1 DATA PROCESSING DEVICE AND DATA PROCESSING METHOD 有权
标题翻译：数据处理设备和数据处理方法
公开(公告)号：US20130166992A1
公开(公告)日：2013-06-27
申请号：US13820808
申请日：2011-09-09
申请人： Yuji Shinohara , Makiko Yamamoto , Lui Sakai
发明人： Yuji Shinohara , Makiko Yamamoto , Lui Sakai
IPC分类号： H03M13/13
CPC分类号： H03M13/13 , H03M13/036 , H03M13/1165 , H03M13/152 , H03M13/255 , H03M13/2707 , H03M13/271 , H03M13/2906 , H03M13/356 , H03M13/6552
摘要： The present invention relates to a data processing device and a data processing method capable of improving the resistance to data error. In a case where an LDPC code having a code length of 4,320 bits is mapped into 16 signal points, when a code bit of 4×2 bits and the (#i+1)-th bit from the most significant bit of symbol bits of 4×2 bits of two consecutive symbols are bits b#i and y#i, a demultiplexer performs an interchange process in which b0 is allocated to y0, b1 is allocated to y4, b2 is allocated to y1, b3 is allocated to y6, b4 is allocated to y2, b5 is allocated to y5, b6 is allocated to y3, and b7 is allocated to y7 for an LDPC code having a coded rate of 1/2, and b0 is allocated to y0, b1 is allocated to y4, b2 is allocated to y5, b3 is allocated to y2, b4 is allocated to y1, b5 is allocated to y6, b6 is allocated to y3, and b7 is allocated to y7 for an LDPC code having a coded rate of 7/12, 2/3, and 3/4. The present invention, for example, can be applied to a transmission system transmitting an LDPC code and the like.
摘要翻译：本发明涉及能够提高数据误差阻力的数据处理装置和数据处理方法。在具有4,320比特的码长的LDPC码被映射到16个信号点的情况下，当4×2比特的码比特和来自符号比特的最高有效位的（＃i + 1）比特两个连续符号的4×2位是位b＃i和y＃i，解复用器执行其中b0被分配给y0的交换处理，b1被分配给y4，b2被分配给y1，b3被分配给y6，将b4分配给y2，将b5分配给y5，将b6分配给y3，将b7分配给y7，对于编码速率为1/2的LDPC码，将b0分配给y0，将b1分配给y4， b2分配给y5，b3分配给y2，b4分配给y1，b5分配给y6，b6分配给y3，b7分配给y7，对于编码率为7/12的LDPC码，2 / 3和3/4。本发明例如可以应用于传输LDPC码等的传输系统。

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