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1. 发明授权

US08410817B2 Driver circuit 失效
标题翻译：驱动电路
公开(公告)号：US08410817B2
公开(公告)日：2013-04-02
申请号：US12858295
申请日：2010-08-17
申请人： Yuji Kuwana , Naoki Matsumoto , Yasuhiro Urabe
发明人： Yuji Kuwana , Naoki Matsumoto , Yasuhiro Urabe
IPC分类号： H03K19/0175 , H03B1/00
CPC分类号： H03K19/001 , H03K17/04126 , H03K19/0136 , H03K2217/0036
摘要： A level switch circuit receives a digital input signal, and generates a level signal having a voltage level that corresponds to the value of the input signal thus received. A buffer circuit receives a level signal, and outputs the level signal via an output terminal thereof. A bias current generating circuit generates a bias current including a DC component having a constant level and a variable component that changes according to the input signal, and supplies the bias current thus generated to a buffer circuit. The bias current generating circuit detects an edge of the input signal, and raises the bias current by a predetermined amount for a predetermined period of time after the edge thus detected.
摘要翻译：电平开关电路接收数字输入信号，并产生具有与所接收的输入信号的值对应的电压电平的电平信号。缓冲电路接收电平信号，并通过其输出端输出电平信号。偏置电流产生电路产生包括具有恒定电平的DC分量和根据输入信号而变化的可变分量的偏置电流，并将由此产生的偏置电流提供给缓冲电路。偏置电流产生电路检测输入信号的边缘，并且在如此检测到的边缘之后的预定时间段内将偏置电流提高预定量。

2. 发明授权

US08013626B2 Test apparatus and driver circuit 有权
标题翻译：测试设备和驱动电路
公开(公告)号：US08013626B2
公开(公告)日：2011-09-06
申请号：US12414681
申请日：2009-03-31
申请人： Yasuhiro Urabe , Naoki Matsumoto , Yuji Kuwana
发明人： Yasuhiro Urabe , Naoki Matsumoto , Yuji Kuwana
IPC分类号： G01R31/02 , G01R31/26
CPC分类号： G01R31/31924 , H04L25/0278
摘要： Provided is a test apparatus that tests a device under test, comprising a driver circuit that generates an output signal according to a prescribed input pattern and supplies the output signal to the device under test; and a measuring section that judges acceptability of the device under test by measuring a response signal output by the device under test. The driver circuit includes an input terminal that receives the input pattern; a switching section that operates according to a logic value of the input pattern to generate the output signal; and an emphasized component generating section that is provided between the input terminal and the switching section, and that (i) generates an emphasized component according to a prescribed high frequency component of the input pattern and (ii) superimposes the emphasized component onto a voltage supplied to the switching section.
摘要翻译：提供了一种测试被测设备的测试装置，包括根据规定的输入模式生成输出信号的驱动电路，并将输出信号提供给被测器件; 以及测量部，其通过测量被测设备输出的响应信号来判断被测设备的可接受性。驱动器电路包括接收输入图案的输入端子; 切换部，其根据所述输入图案的逻辑值进行动作，生成所述输出信号; 以及设置在所述输入端子和所述开关部分之间的强调分量产生部分，以及（i）根据所述输入图案的规定的高频分量产生强调分量，以及（ii）将所述强调分量叠加到所提供的电压到切换部分。

3. 发明申请

US20100244880A1 TEST APPARATUS AND DRIVER CIRCUIT 失效
标题翻译：测试装置和驱动电路
公开(公告)号：US20100244880A1
公开(公告)日：2010-09-30
申请号：US12412364
申请日：2009-03-27
申请人： Yasuhiro Urabe , Naoki Matsumoto , Yuji Kuwana
发明人： Yasuhiro Urabe , Naoki Matsumoto , Yuji Kuwana
IPC分类号： G01R31/26 , H03B1/00
CPC分类号： G01R31/2889 , G01R31/31924
摘要： Provided is a test apparatus that tests a device under test, comprising a driver circuit that generates an output signal according to a prescribed input pattern, and supplies the output signal to the device under test; and a measuring section that measures a response signal output by the device under test to judge the acceptability of the device under test, wherein the driver circuit includes an input gate drive section that selects one of a plurality of input drive voltages supplied thereto, according to a logic value of the input pattern, and outputs the selected input drive voltage; a voltage switching section that includes a transistor and that outputs the output signal according to the drain voltage of the transistor, the transistor having a gate terminal that receives the input drive voltage output by the input gate drive section and a source terminal to which is applied a prescribed reference voltage; and an input drive voltage supplying section that generates the input drive voltages according to the reference voltage, and supplies the input drive voltages to the input gate drive section.
摘要翻译：提供了一种测试被测设备的测试装置，包括根据规定的输入模式产生输出信号的驱动电路，并将输出信号提供给被测器件; 以及测量部，其测量由所述被测设备输出的响应信号，判断被测设备的可接受性，其中，所述驱动电路包括：输入栅极驱动部，其根据所述输入栅极驱动部选择供给的多个输入驱动电压中的一个，输入图案的逻辑值，并输出所选择的输入驱动电压; 电压切换部，其包括晶体管，并且根据所述晶体管的漏极电压输出所述输出信号，所述晶体管具有接收由所述输入栅极驱动部输出的输入驱动电压的栅极端子和施加到所述输入栅极驱动部的源极端子规定的参考电压; 以及输入驱动电压供给部，其根据所述基准电压生成所述输入驱动电压，并将所述输入驱动电压提供给所述输入栅极驱动部。

4. 发明授权

US07795897B1 Test apparatus and driver circuit 失效
标题翻译：测试设备和驱动电路
公开(公告)号：US07795897B1
公开(公告)日：2010-09-14
申请号：US12412364
申请日：2009-03-27
申请人： Yasuhiro Urabe , Naoki Matsumoto , Yuji Kuwana
发明人： Yasuhiro Urabe , Naoki Matsumoto , Yuji Kuwana
IPC分类号： G01R31/26
CPC分类号： G01R31/2889 , G01R31/31924
摘要： Provided is a test apparatus that tests a device under test, comprising a driver circuit that generates an output signal according to a prescribed input pattern, and supplies the output signal to the device under test; and a measuring section that measures a response signal output by the device under test to judge the acceptability of the device under test, wherein the driver circuit includes an input gate drive section that selects one of a plurality of input drive voltages supplied thereto, according to a logic value of the input pattern, and outputs the selected input drive voltage; a voltage switching section that includes a transistor and that outputs the output signal according to the drain voltage of the transistor, the transistor having a gate terminal that receives the input drive voltage output by the input gate drive section and a source terminal to which is applied a prescribed reference voltage; and an input drive voltage supplying section that generates the input drive voltages according to the reference voltage, and supplies the input drive voltages to the input gate drive section.
摘要翻译：提供了一种测试被测设备的测试装置，包括根据规定的输入模式产生输出信号的驱动电路，并将输出信号提供给被测器件; 以及测量部，其测量由所述被测设备输出的响应信号，判断被测设备的可接受性，其中，所述驱动电路包括：输入栅极驱动部，其根据所述输入栅极驱动部选择供给的多个输入驱动电压中的一个，输入图案的逻辑值，并输出所选择的输入驱动电压; 电压切换部，其包括晶体管，并且根据所述晶体管的漏极电压输出所述输出信号，所述晶体管具有接收由所述输入栅极驱动部输出的输入驱动电压的栅极端子和施加到所述输入栅极驱动部的源极端子规定的参考电压; 以及输入驱动电压供给部，其根据所述基准电压生成所述输入驱动电压，并将所述输入驱动电压提供给所述输入栅极驱动部。

5. 发明授权

US08368366B2 Driver circuit and test apparatus 失效
标题翻译：驱动电路和测试仪器
公开(公告)号：US08368366B2
公开(公告)日：2013-02-05
申请号：US12553755
申请日：2009-09-03
申请人： Yuji Kuwana , Naoki Matsumoto , Yasuhiro Urabe
发明人： Yuji Kuwana , Naoki Matsumoto , Yasuhiro Urabe
IPC分类号： G05F1/40
CPC分类号： H03F3/45
摘要： Provided is a driver circuit that outputs, from an output end, an output signal corresponding to an input signal supplied thereto, comprising an output resistance section that is provided between a constant voltage source and the output end; an output switching section that switches voltage of the output end according to the input signal; and a switching section that switches a resistance value of the output resistance section. The output resistance section includes an output resistance FET having a source/drain connection between the constant voltage source and the output end, and the switching section supplies a control voltage to a gate of the output resistance FET such that the resistance between the source and the drain of the output resistance FET switches to a designated value.
摘要翻译：提供了一种从输出端输出与提供给其的输入信号相对应的输出信号的驱动器电路，包括设置在恒定电压源和输出端之间的输出电阻部分; 输出切换部，其根据输入信号切换输出端的电压; 以及切换部，切换输出电阻部的电阻值。输出电阻部分包括在恒定电压源和输出端之间具有源极/漏极连接的输出电阻FET，并且开关部分向输出电阻FET的栅极提供控制电压，使得源极和源极之间的电阻输出电阻FET的漏极切换到指定值。

6. 发明授权

US08531187B2 Compensation circuit and test apparatus 失效
标题翻译：补偿电路和测试仪器
公开(公告)号：US08531187B2
公开(公告)日：2013-09-10
申请号：US12652550
申请日：2010-01-05
申请人： Yuji Kuwana , Naoki Matsumoto
发明人： Yuji Kuwana , Naoki Matsumoto
IPC分类号： H03K19/0175
CPC分类号： G01R31/31924 , G01R31/3191
摘要： Provided is a correction circuit for generating an output signal emphasizing a predetermined signal component of a supplied input signal, including: a first detection section that detects a waveform of the input signal; an amplifying section that amplifies the waveform detected by the first detection section; a correction signal generating section that generates a correction signal by extracting an alternate current component from the waveform amplified by the amplifying section; and an output signal generating section that superimposes the correction signal on the waveform of the input signal, thereby generating the output signal. The first detection section detects the waveform of the input signal and an inverted waveform thereof, the amplifying section amplifies the waveform and the inverted waveform of the input signal, the correction signal generating section generates a correction signal and an inverted correction signal by extracting an alternate current component respectively of the waveform and the inverted waveform of the input signal amplified by the amplifying section, and the output signal generating section generates a pair of differential signals for the output signal, by superimposing the correction signal on the waveform of the input signal and superimposing the inverted correction signal on the inverted waveform of the input signal.
摘要翻译：提供了一种用于产生强调所提供的输入信号的预定信号分量的输出信号的校正电路，包括：第一检测部分，其检测输入信号的波形; 放大部，其放大由所述第一检测部检测出的波形; 校正信号生成部，其从由放大部放大的波形中提取交流分量，生成校正信号; 以及输出信号生成部，其将所述校正信号叠加在所述输入信号的波形上，从而生成所述输出信号。第一检测部分检测输入信号的波形及其反相波形，放大部分放大输入信号的波形和反相波形，校正信号产生部分通过提取交替的方式产生校正信号和反相校正信号分别由放大部分放大的输入信号的波形和反相波形的电流分量，并且输出信号产生部分通过将校正信号叠加在输入信号的波形上并产生一对差分信号用于输出信号，将反相校正信号叠加在输入信号的反相波形上。

7. 发明授权

US08920596B2 Plasma processing apparatus 有权
标题翻译：等离子体处理装置
公开(公告)号：US08920596B2
公开(公告)日：2014-12-30
申请号：US12862915
申请日：2010-08-25
申请人： Naoki Mihara , Naoki Matsumoto , Jun Yoshikawa , Kazuo Murakami
发明人： Naoki Mihara , Naoki Matsumoto , Jun Yoshikawa , Kazuo Murakami
IPC分类号： H01L21/3065 , H01J37/32
CPC分类号： H01J37/32192 , C23C16/513 , H01J37/3244 , H01J37/32449
摘要： In a plasma processing apparatus for processing a substrate by plasmatizing a process gas introduced into a processing container, an introducing unit which introduces the process gas is formed on a ceiling surface of the processing container; a gas retention portion which gathers the process gas supplied from the outside of the processing container through a supply passage, and a plurality of gas ejection holes which allow communication between the gas retention portion and the inside of the processing container are formed in the introducing unit; a gas ejection hole is not formed in a location of the gas retention portion that faces an opening of the supply passage; and a cross section of each of the gas ejection holes has a flat shape.
摘要翻译：在通过对引入到处理容器中的处理气体进行等离子体处理衬底的等离子体处理装置中，在处理容器的顶表面上形成引入处理气体的引入单元; 气体保持部，其通过供给通路收集从处理容器的外部供给的处理气体，并且在导入单元中形成有能够使气体保持部与处理容器内部连通的多个气体喷出孔 ; 在气体保持部的与供给通道的开口相对的位置处不形成气体喷出孔; 并且每个气体喷射孔的横截面具有扁平形状。

8. 发明授权

US08877004B2 Plasma processing apparatus and plasma processing method 有权
标题翻译：等离子体处理装置和等离子体处理方法
公开(公告)号：US08877004B2
公开(公告)日：2014-11-04
申请号：US12866545
申请日：2009-02-06
申请人： Naoki Matsumoto , Kazuyuki Kato , Masafumi Shikata , Masaru Sasaki
发明人： Naoki Matsumoto , Kazuyuki Kato , Masafumi Shikata , Masaru Sasaki
IPC分类号： C23C16/00 , C23F1/00 , H01L21/306 , H01J37/32 , H05H1/46
CPC分类号： H05H1/46 , H01J37/32192 , H01J37/32238
摘要： A dielectric plate 20 is provided at a ceiling surface facing a susceptor 3 of a processing chamber 2, and a slot antenna 30 having a multiple number of microwave transmissive slots 33 is provided on a top surface of the dielectric plate 20. A protrusion member 21 configured as a separate member from the dielectric plate 20 is provided on a peripheral portion of a bottom surface of the dielectric plate 20 so as to prevent an abnormal electric discharge. Electric field intensity in the vicinity of the dielectric plate 20 is controlled by adjusting a gap between an outer peripheral surface 22 of a cylindrical part of the protrusion member 21 and an inner peripheral surface 5a of a sidewall of the processing chamber 2 or by adjusting a thickness of the cylindrical part of the protrusion member 21.
摘要翻译：电介质板20设置在面向处理室2的基座3的顶面上，并且具有多个微波透射槽33的缝隙天线30设置在电介质板20的顶表面上。突起构件21 在电介质板20的底面的周边部设置有与电介质板20分离的部件，以防止异常放电。通过调整突起部件21的圆筒部的外周面22与处理室2的侧壁的内周面5a之间的间隙，调整电介质板20附近的电场强度，突出部件21的圆筒部的厚度。

9. 发明授权

US08617865B2 Tannase, gene encoding same, and process for producing same 有权
标题翻译：鞣酸酶，编码基因的基因及其制备方法
公开(公告)号：US08617865B2
公开(公告)日：2013-12-31
申请号：US13124510
申请日：2009-10-02
申请人： Megumi Nakagawa , Naoki Matsumoto , Hitoshi Amano , Shotaro Yamaguchi
发明人： Megumi Nakagawa , Naoki Matsumoto , Hitoshi Amano , Shotaro Yamaguchi
IPC分类号： C12N9/14
CPC分类号： C12N9/18 , C12P7/42
摘要： Disclosed is a thermostable tannase derived from a microorganism. Specifically disclosed is a thermostable tannase derived from Aspergillus awamori or Aspergillus niger. A preferred embodiment of the tannase has the following chemoenzymatic properties: (1) activity: to act on a depside bond to thereby cause hydrolysis; (2) molecular weight: about 230,000 Da (as measured by gel filtration); and (3) thermal stability: stable at a temperature up to 65° C. (pH 5.0, 30 min.)
摘要翻译：公开了一种衍生自微生物的热稳定性鞣酸酶。具体公开了源自泡盛曲霉或黑曲霉的热稳定性鞣酸酶。鞣酸酶的优选实施方案具有以下化学酶学性质：（1）活性：作用于脱附键从而引起水解; （2）分子量：约230,000Da（通过凝胶过滤测量）; 和（3）热稳定性：在高达65℃的温度下稳定（pH5.0,30分钟）

10. 外观设计

USD694791S1 Baffle plate for manufacturing semiconductor 有权
公开(公告)号：USD694791S1
公开(公告)日：2013-12-03
申请号：US29416088
申请日：2012-03-19
申请人： Naoki Matsumoto , Jun Yoshikawa
设计人： Naoki Matsumoto , Jun Yoshikawa

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