专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060274850A1 Digital data transmitting apparatus 失效
公开(公告)号：US20060274850A1
公开(公告)日：2006-12-07
申请号：US10569274
申请日：2004-09-07
申请人： Yuji Kasai , Maria Murakawa , Tetsuya Higuchi
发明人： Yuji Kasai , Maria Murakawa , Tetsuya Higuchi
IPC分类号： H04L25/49
CPC分类号： H04L27/368 , H04L5/14 , H04L25/03343
摘要： A transmitting circuit 10 converts transmission data to a multilevel analog signal suitable for transmission. The multilevel analog signal is output to a cable 21 via an amplifier and a hybrid circuit 12. In the transmitting circuit 10, a waveform which compensates waveform deterioration at the cable 21 is generated. A reception signal from the cable 21 is input to a mixer 14 via the hybrid circuit 12 and an amplifier 13. The mixer 14 mixes the reception signal and a cancel signal output from a cancel signal generation circuit 17 so as to remove undesired signals. In a receiving circuit 15, the signal output from the mixer 14 is sampled by use of a plurality of sample-hold circuits, and subjected to analog sum-of-product computation which is performed by a matrix circuit for distortion compensation. Subsequently, the sampled signals are converted to digital signals. The digital signals are collectively subjected to processing such as parallel-serial conversion, whereby reception data and an evaluation signal are obtained. An adjustment control circuit 18 includes a CPU, and adjusts the respective circuits on the basis of the evaluation signal such that data can be correctly transmitted and received.

2. 发明授权

US07274238B2 Digital circuit having delay circuit for adjustment of clock signal timing 有权
标题翻译：具有用于调整时钟信号定时的延迟电路的数字电路
公开(公告)号：US07274238B2
公开(公告)日：2007-09-25
申请号：US10520429
申请日：2003-07-08
申请人： Eiichi Takahashi , Yuji Kasai , Tetsuya Higuchi
发明人： Eiichi Takahashi , Yuji Kasai , Tetsuya Higuchi
IPC分类号： H03H11/26
CPC分类号： H03L7/07 , H03K5/133 , H03K2005/00026 , H03L7/0805 , H03L7/0812
摘要： A digital circuit according to the present invention includes a pulse delay circuit where a driving current of an inverter is variable, for causing timing of a clock signal to be variable; and the pulse delay circuit has a stabilizing circuit for an amount of a pulse delay by a delay synchronizing loop, and a generating circuit for a pulse delay amount setting voltage with nonlinear characteristics. The present invention makes it possible to realize a timing delay circuit with high resolution, which is not influenced by an operating environment and requires only a small area for the circuit.
摘要翻译：根据本发明的数字电路包括脉冲延迟电路，其中逆变器的驱动电流是可变的，用于使时钟信号的定时可变; 并且脉冲延迟电路具有用于通过延迟同步环路的脉冲延迟量的稳定电路，以及具有非线性特性的脉冲延迟量设定电压的发生电路。本发明使得可以实现不受操作环境影响的高分辨率的定时延迟电路，并且仅需要较小的电路面积。

3. 发明授权

US08982926B2 Spectrum spread communication system 有权
标题翻译：频谱传播通信系统
公开(公告)号：US08982926B2
公开(公告)日：2015-03-17
申请号：US13704087
申请日：2011-06-06
申请人： Yuji Kasai , Masahiro Murakawa , Tetsuya Higuchi
发明人： Yuji Kasai , Masahiro Murakawa , Tetsuya Higuchi
IPC分类号： H04B1/00 , H04B1/7075 , H04B1/707 , H04B3/54 , H04J13/16 , H04B1/7073
CPC分类号： H04B1/7075 , H04B1/707 , H04B1/7073 , H04B1/70735 , H04B3/542 , H04B2203/5416 , H04J13/16
摘要： Disclosed is a spectrum spread communication system which is hardly influenced by noises, and in which a frame structure can be identified at a receiving side without use of a frame synchronization signal. A spread code generator switches spread codes (“Scai” and “Scbi”) in each frame, and outputs it to a spread modulation unit. The spread modulation unit performs spread modulation of transmission data, and transmits it to a direct current power line. A reference code generator generates reference codes (“Scai” and “Scbi”) in the same code phase. Spread demodulation units performs spread demodulation of the received signal with use of the reference codes (“Scai” and “Scbi”), and output it to a selection unit. A frame synchronization detection unit identifies a frame structure on the basis of switching of a synchronization state of a code phase in a code phase synchronization detection unit. The selection unit outputs reception data by selecting spread demodulated data from the spread demodulation unit which is in a phase-synchronized state.
摘要翻译：公开了几乎不受噪声影响的频谱扩展通信系统，其中可以在接收侧识别帧结构而不使用帧同步信号。扩展码发生器在每帧中切换扩展码（“Scai”和“Scbi”），并将其输出到扩展调制单元。扩展调制单元执行发送数据的扩展调制，并将其发送到直流电力线。参考代码生成器在相同的代码阶段生成参考代码（“Scai”和“Scbi”）。扩展解调单元使用参考码（“Scai”和“Scbi”）对接收信号进行扩展解调，并将其输出到选择单元。帧同步检测单元基于码相位同步检测单元中的码相位的同步状态的切换来识别帧结构。选择单元通过从相位同步状态的扩展解调单元中选择扩展解调数据来输出接收数据。

4. 发明授权

US07295032B2 High-speed signal transmission system 失效
标题翻译：高速信号传输系统
公开(公告)号：US07295032B2
公开(公告)日：2007-11-13
申请号：US10511720
申请日：2003-04-21
申请人： Kanji Otsuka , Tamotsu Usami , Tetsuya Higuchi , Eiichi Takahashi , Yuji Kasai , Masahiro Murakawa
发明人： Kanji Otsuka , Tamotsu Usami , Tetsuya Higuchi , Eiichi Takahashi , Yuji Kasai , Masahiro Murakawa
IPC分类号： H03K17/16
CPC分类号： H04B3/04 , H01L2224/48227 , H01L2924/12032 , H01L2924/1305 , H01L2924/13091 , H01L2924/19107 , H04L25/0286 , H01L2924/00
摘要： A purpose of a high-speed signal transmission system of the present invention is to pass a high-speed digital signal through an outside-chip line exchanging a signal with a high speed LSI chip with a band higher than GHz. The high-speed signal transmission system of the present invention has a configuration of: insertion of a circuit for feeding back received information and adjusting a waveform at a sending side based on genetic algorithm; a device structure for automatically performing pump up and pump down of a transistor carrier; a transmission line of a wiring out of a transistor; and elimination of a common power source of a circuit.
摘要翻译：本发明的高速信号传输系统的目的是通过外部芯片线路将高速数字信号与具有高于GHz的频带的高速LSI芯片交换信号。本发明的高速信号传输系统具有以下结构：基于遗传算法插入用于反馈接收信息的电路和调整发送侧的波形; 用于自动地执行泵浦和泵浦晶体管载体的装置结构; 晶体管的布线传输线; 并消除电路的公共电源。

5. 发明申请

US20060109146A1 Digital circuit having a delay circuit for adjustment of clock signal timing 有权
标题翻译：具有用于调整时钟信号定时的延迟电路的数字电路
公开(公告)号：US20060109146A1
公开(公告)日：2006-05-25
申请号：US10520429
申请日：2003-07-08
申请人： Eiichi Takahashi , Yuji Kasai , Tetsuya Higuchi
发明人： Eiichi Takahashi , Yuji Kasai , Tetsuya Higuchi
IPC分类号： H03M7/00
CPC分类号： H03L7/07 , H03K5/133 , H03K2005/00026 , H03L7/0805 , H03L7/0812
摘要： A digital circuit according to the present invention includes a pulse delay circuit where a driving current of an inverter is variable, for causing timing of a clock signal to be variable; and the pulse delay circuit has a stabilizing circuit for an amount of a pulse delay by a delay synchronizing loop, and a generating circuit for a pulse delay amount setting voltage with nonlinear characteristics. The present invention makes it possible to realize a timing delay circuit with high resolution, which is not influenced by an operating environment and requires only a small area for the circuit.
摘要翻译：根据本发明的数字电路包括脉冲延迟电路，其中逆变器的驱动电流是可变的，用于使时钟信号的定时可变; 并且脉冲延迟电路具有用于通过延迟同步环路的脉冲延迟量的稳定电路，以及具有非线性特性的脉冲延迟量设定电压的发生电路。本发明使得可以实现不受操作环境影响的高分辨率的定时延迟电路，并且仅需要较小的电路面积。

6. 发明授权

US06879388B2 Optical apparatus, optical apparatus adjustment method, and storage medium recorded with a processing program that executes said adjustment method 失效
标题翻译：光学装置，光学装置调整方法以及记录有执行所述调整方法的处理程序的存储介质
公开(公告)号：US06879388B2
公开(公告)日：2005-04-12
申请号：US10866113
申请日：2004-06-14
申请人： Yuji Kasai , Masahiro Murakawa , Taro Itatani , Tetsuya Higuchi
发明人： Yuji Kasai , Masahiro Murakawa , Taro Itatani , Tetsuya Higuchi
IPC分类号： G06F15/18 , G02B7/00 , G02B23/02 , G02B27/62 , G06N3/00 , H01S3/06 , H01S3/086 , H01S3/139 , G01B11/26
CPC分类号： G02B7/005 , G02B27/62
摘要： An optical apparatus has an adjustment apparatus 5 and an optical unit 1 including a plurality of optical elements. The adjustment apparatus sequentially provides control signals that, according to a probabilistic search technique, change the parameters of a stipulated plurality of optical elements among the optical elements to become parameters that cause the functions of the optical apparatus to satisfy stipulated specifications. A method of adjusting the optical apparatus includes sequentially providing control signals that, according to a probabilistic search technique, change the parameters of the stipulated plurality of optical elements among the optical elements, and searching for optical values at which the functions of the optical apparatus the stipulated specification.
摘要翻译：光学装置具有调整装置5和包括多个光学元件的光学单元1。调整装置顺序地提供控制信号，根据概率检索技术，改变光学元件中规定的多个光学元件的参数，成为使光学装置的功能满足规定规格的参数。调整光学装置的方法包括依次提供控制信号，根据概率检索技术，改变光学元件中规定的多个光学元件的参数，并且搜索光学装置的功能的光学值规定的规格。

7. 发明授权

US06781682B1 Optical apparatus, optical apparatus adjustment method, and storage medium recorded with a processing program that executes said adjustment method 失效
公开(公告)号：US06781682B1
公开(公告)日：2004-08-24
申请号：US09536620
申请日：2000-03-28
申请人： Yuji Kasai , Masahiro Murakawa , Taro Itatani , Tetsuya Higuchi
发明人： Yuji Kasai , Masahiro Murakawa , Taro Itatani , Tetsuya Higuchi
IPC分类号： G01B1126
CPC分类号： G02B7/005 , G02B27/62
摘要： An optical apparatus has an adjustment apparatus 5 and an optical unit 1 including a plurality of optical elements. The adjustment apparatus sequentially provides control signals that, according to a probabilistic search technique, change the parameters of a stipulated plurality of optical elements among the optical elements to become parameters that cause the functions of the optical apparatus to satisfy stipulated specifications. A method of adjusting the optical apparatus includes sequentially providing control signals that, according to a probabilistic search technique, change the parameters of the stipulated plurality of optical elements among the optical elements, and searching for optical values at which the functions of the optical apparatus the stipulated specification.

8. 发明申请

US20130089120A1 SPECTRUM SPREAD COMMUNICATION SYSTEM 有权
标题翻译：光谱传播通信系统
公开(公告)号：US20130089120A1
公开(公告)日：2013-04-11
申请号：US13704087
申请日：2011-06-06
申请人： Yuji Kasai , Masahiro Murakawa , Tetsuya Higuchi
发明人： Yuji Kasai , Masahiro Murakawa , Tetsuya Higuchi
IPC分类号： H04B1/7075
CPC分类号： H04B1/7075 , H04B1/707 , H04B1/7073 , H04B1/70735 , H04B3/542 , H04B2203/5416 , H04J13/16
摘要： Disclosed is a spectrum spread communication system which is hardly influenced by noises, and in which a frame structure can be identified at a receiving side without use of a frame synchronization signal. A spread code generator switches spread codes (“Scai” and “Scbi”) in each frame, and outputs it to a spread modulation unit. The spread modulation unit performs spread modulation of transmission data, and transmits it to a direct current power line. A reference code generator generates reference codes (“Scai” and “Scbi”) in the same code phase. Spread demodulation units performs spread demodulation of the received signal with use of the reference codes (“Scai” and “Scbi”), and output it to a selection unit. A frame synchronization detection unit identifies a frame structure on the basis of switching of a synchronization state of a code phase in a code phase synchronization detection unit. The selection unit outputs reception data by selecting spread demodulated data from the spread demodulation unit which is in a phase-synchronized state.
摘要翻译：公开了几乎不受噪声影响的频谱扩展通信系统，其中可以在接收侧识别帧结构而不使用帧同步信号。扩频码发生器在每帧中切换扩频码（Scai和Scbi），并将其输出到扩展调制单元。扩展调制单元执行发送数据的扩展调制，并将其发送到直流电力线。参考代码生成器在相同的代码阶段生成参考代码（Scai和Scbi）。扩展解调单元使用参考码（Scai和Scbi）对接收信号进行扩展解调，并将其输出到选择单元。帧同步检测单元基于码相位同步检测单元中的码相位的同步状态的切换来识别帧结构。选择单元通过从相位同步状态的扩展解调单元中选择扩展解调数据来输出接收数据。

9. 发明申请

US20110142066A1 SERIAL BUS TRANSMISSION SYSTEM 有权
标题翻译：串行总线传输系统
公开(公告)号：US20110142066A1
公开(公告)日：2011-06-16
申请号：US12988939
申请日：2009-04-20
申请人： Yuji Kasai , Eiichi Takahashi , Masahiro Murakawa , Tetsuya Higuchi
发明人： Yuji Kasai , Eiichi Takahashi , Masahiro Murakawa , Tetsuya Higuchi
IPC分类号： H04B7/212
CPC分类号： H04L12/4035
摘要： A master node (12) sends an identification signal for designating a communication channel in an identification signal time slot. When the own node matches the node in which the communication channel designated by the identification signal sent from the master node (12) is set in the identification signal time slot, the master node (12) and slave nodes (131 to 13n) each perform data transmission via the communication channel, based on the set contents of the communication channel, in the data transmission time slot corresponding to the identification signal time slot in which the identification signal has been sent.
摘要翻译：主节点（12）在识别信号时隙中发送用于指定通信信道的识别信号。当自身节点与在主节点（12）发送的识别信号指定的通信信道被设置在识别信号时隙中的节点匹配时，主节点（12）和从节点（131至13n）各自执行在与发送识别信号的识别信号时隙对应的数据传输时隙中，基于通信信道的设定内容，经由通信信道的数据传输。

10. 发明授权

US07447289B2 Signal timing adjustment device, signal timing adjustment system, signal timing adjustment amount setting program, and storage medium storing the program 失效
标题翻译：信号定时调整装置，信号定时调整系统，信号定时调整量设定程序以及存储该程序的存储介质
公开(公告)号：US07447289B2
公开(公告)日：2008-11-04
申请号：US10809374
申请日：2004-03-26
申请人： Munehiro Uratani , Eiichi Takahashi , Yuji Kasai , Tetsuya Higuchi , Masahiro Murakawa
发明人： Munehiro Uratani , Eiichi Takahashi , Yuji Kasai , Tetsuya Higuchi , Masahiro Murakawa
IPC分类号： H04L7/00
CPC分类号： H04L7/0337 , H03L7/087
摘要： Delay time between an input of data to a circuit block and an output of the data from the data block is measured in accordance with a timing at which the data from the circuit block is acquired by a measurement register and a timing at which the data from the circuit block is acquired by a data latch. An LSI tester sets well voltage adjustment values so that delay time of each circuit block is averaged. From voltages generated by the adjustment voltage generating circuit, a selector selects voltages that are in accordance with the well voltage adjustment values. The voltages selected are applied to a well of a CMOS transistor of each clock timing adjustment circuit. Delay time between timings of inputted clocks is thus adjusted.
摘要翻译：根据来自电路块的数据通过测量寄存器获取的定时和来自数据块的数据的定时，测量数据到电路块的数据输入与来自数据块的数据的输出之间的延迟时间电路块由数据锁存器获取。 LSI测试仪设置好的电压调整值，使得每个电路块的延迟时间被平均。根据由调整电压产生电路产生的电压，选择器选择与电压调节值相一致的电压。所选择的电压被施加到每个时钟定时调整电路的CMOS晶体管的阱。因此调整输入时钟的定时之间的延迟时间。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式