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    • 6. 发明授权
    • Nonvolatile semiconductor memory device
    • 非易失性半导体存储器件
    • US07791943B2
    • 2010-09-07
    • US12571917
    • 2009-10-01
    • Motoharu IshiiSeiichi Endo
    • Motoharu IshiiSeiichi Endo
    • G11C11/34
    • G11C16/3468G11C16/344G11C16/3445G11C16/3477H01L27/11526H01L27/11529
    • In a nonvolatile memory cell, a selection transistor is connected to a memory cell transistor in series. The selection transistor is formed into a double layer gate structure, and has a voltage of each gate driven individually and separately. Using capacitive coupling between these stacked gate electrode layers of the selection transistor, a gate potential of the selection transistor is set to the predetermined voltage level. An absolute value of the voltage level generated by a voltage generator to the gates of the selection transistor can be made small, so that current consumption can be reduced and an layout area of the voltage generator can be reduced. Thus, a nonvolatile semiconductor memory device with a low current consumption and a small chip layout area is provided.
    • 在非易失性存储单元中,选择晶体管串联连接到存储单元晶体管。 选择晶体管形成双层栅极结构,并且每个栅极的电压分别驱动。 使用选择晶体管的这些叠层栅极电极层之间的电容耦合,将选择晶体管的栅极电位设置为预定电压电平。 可以使由电压发生器对选择晶体管的栅极产生的电压电平的绝对值较小,从而可以减少电流消耗,并且可以减小电压发生器的布局面积。 因此,提供了具有低电流消耗和小芯片布局面积的非易失性半导体存储器件。
    • 9. 发明申请
    • NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
    • 非易失性半导体存储器件
    • US20100014355A1
    • 2010-01-21
    • US12571917
    • 2009-10-01
    • Motoharu IshiiSeiichi Endo
    • Motoharu IshiiSeiichi Endo
    • G11C16/04
    • G11C16/3468G11C16/344G11C16/3445G11C16/3477H01L27/11526H01L27/11529
    • In a nonvolatile memory cell, a selection transistor is connected to a memory cell transistor in series. The selection transistor is formed into a double layer gate structure, and has a voltage of each gate driven individually and separately. Using capacitive coupling between these stacked gate electrode layers of the selection transistor, a gate potential of the selection transistor is set to the predetermined voltage level. An absolute value of the voltage level generated by a voltage generator to the gates of the selection transistor can be made small, so that current consumption can be reduced and an layout area of the voltage generator can be reduced. Thus, a nonvolatile semiconductor memory device with a low current consumption and a small chip layout area is provided.
    • 在非易失性存储单元中,选择晶体管串联连接到存储单元晶体管。 选择晶体管形成双层栅极结构,并且每个栅极的电压分别驱动。 使用选择晶体管的这些叠层栅极电极层之间的电容耦合,将选择晶体管的栅极电位设置为预定电压电平。 可以使由电压发生器对选择晶体管的栅极产生的电压电平的绝对值较小,从而可以减少电流消耗,并且可以减小电压发生器的布局面积。 因此,提供了具有低电流消耗和小芯片布局面积的非易失性半导体存储器件。