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1. 发明申请

US20060224715A1 Computer management program, managed computer control program, computer management apparatus, managed computer, computer management system, computer management method, and managed computer control method 审中-公开
标题翻译：计算机管理程序，管理计算机控制程序，计算机管理装置，管理计算机，计算机管理系统，计算机管理方法和管理计算机控制方法
公开(公告)号：US20060224715A1
公开(公告)日：2006-10-05
申请号：US11336935
申请日：2006-01-23
申请人： Yuichiro Ajima , Akihiro Yasuo , Yoshiro Ikeda , Atsushi Mori
发明人： Yuichiro Ajima , Akihiro Yasuo , Yoshiro Ikeda , Atsushi Mori
IPC分类号： G06F15/173
CPC分类号： H04L43/0817 , H04L41/044
摘要： The present invention has been made to provide a computer management program, a managed computer control program, a computer management apparatus, a managed computer, a computer management system, a computer management method, and a managed computer control method allowing the management agent to easily perform autonomous communication frequency control. A computer management program allowing a computer to execute: a communication processing step that receives a request message from the managed computer, writes information from the managed computer in a management registry, and reads out information for the managed computer from the management registry so as to transmit a result of the readout operation to the managed computer as a reply message; and a management processing step that reads out information from the managed computer in the management registry, performs management processing for the managed computer according to a result of the readout operation, and writes information for the managed computer, which is to be obtained by a result of the management processing, in the management registry.
摘要翻译：本发明是为了提供计算机管理程序，被管理计算机控制程序，计算机管理装置，被管理计算机，计算机管理系统，计算机管理方法和管理计算机控制方法，允许管理代理人容易地执行自主通信频率控制。一种允许计算机执行的计算机管理程序：通信处理步骤，从所述被管理计算机接收请求消息，将来自所述被管理计算机的信息写入管理注册表，并从所述管理注册表读出所述被管理计算机的信息，以便将读出操作的结果作为回复消息发送到被管理计算机; 以及管理处理步骤，从管理注册表中的被管理计算机读出信息，根据读出操作的结果对被管理计算机执行管理处理，并且将由被检索的计算机写入信息，该信息将通过结果获得的管理处理，在管理注册表中。

2. 发明授权

US10430375B2 Parallel computing system and communication control program 有权
公开(公告)号：US10430375B2
公开(公告)日：2019-10-01
申请号：US12872338
申请日：2010-08-31
申请人： Yuichiro Ajima , Toshiyuki Shimizu , Hiroaki Ishihata
发明人： Yuichiro Ajima , Toshiyuki Shimizu , Hiroaki Ishihata
IPC分类号： G06F15/80
摘要： A parallel computing system includes a plurality of processors multi-dimensionally commented by an interconnection network, wherein each of the processors in the parallel computing system determines, in dimensional order, communication channels to other processors in the interconnection network, each of the processors sets, as relative coordinates of destination processors with respect to the plurality of processors in data communications performed at a same timing, relative coordinates common to all of the processors, and each of the processors performs data communications with destination processors having the set relative coordinates.

3. 发明授权

US09143436B2 Information processing apparatus, parallel computer system, and control method of parallel computer system 有权
标题翻译：信息处理装置，并行计算机系统和并行计算机系统的控制方法
公开(公告)号：US09143436B2
公开(公告)日：2015-09-22
申请号：US13359635
申请日：2012-01-27
申请人： Shinya Hiramoto , Yuichiro Ajima , Tomohiro Inoue
发明人： Shinya Hiramoto , Yuichiro Ajima , Tomohiro Inoue
IPC分类号： H04L12/801 , H04L12/729 , H04L12/727 , H04L12/721 , H04L12/26
CPC分类号： H04L45/125 , H04L43/0882 , H04L45/121 , H04L45/127 , H04L45/70 , H04L47/115
摘要： An information processing apparatus connected to another information apparatus in a parallel computer system via a plurality of routes, includes: an arithmetic processing device to issue an instruction for collection of congestion information and for communication; a route information holding unit to hold route information for performing communication; a transmission unit to transmit a congestion information collection packet to any of the plurality of routes; a reception unit to receive a congestion information collection response packet corresponding to the congestion information collection packet from any of the plurality of routes; and a control unit to cause the transmission unit to transmit a congestion information collection packet, to select route information from the route information holding unit based on congestion information included in the congestion information collection response packet, and to cause the transmission unit to perform communication instructed by the arithmetic processing device based on the selected route information.
摘要翻译：一种信息处理装置，其通过多条路径与并行计算机系统中的另一信息装置连接，包括：发出用于收集拥塞信息和通信的指令的运算处理装置; 路由信息保持单元，保存用于进行通信的路由信息; 发送单元，向所述多个路由中的任一个发送拥塞信息收集分组; 接收单元，用于从所述多个路由中的任一个接收与所述拥塞信息收集分组相对应的拥塞信息收集响应分组; 以及控制单元，用于使所述发送单元发送拥塞信息收集包，基于所述拥挤信息收集响应包中包含的拥塞信息，从所述路径信息保持单元选择路由信息，并使所述发送单元进行通信指示由算术处理装置基于所选择的路线信息。

4. 发明授权

US08504731B2 Network for interconnecting computers 有权
标题翻译：网络互联电脑
公开(公告)号：US08504731B2
公开(公告)日：2013-08-06
申请号：US12942291
申请日：2010-11-09
申请人： Yuichiro Ajima , Tomohiro Inoue , Shinya Hiramoto
发明人： Yuichiro Ajima , Tomohiro Inoue , Shinya Hiramoto
IPC分类号： G06F15/16
CPC分类号： G06F15/16 , G06F15/17337
摘要： In a parallel computer system including a plurality of processors, processors are classified into a plurality of groups including a prescribed number of processors, and processors are connected to each other in a complete connecting manner in the groups. Those groups are connected to each other as the respective processors are connected in linear to each other.
摘要翻译：在包括多个处理器的并行计算机系统中，将处理器分为包括规定数量的处理器的多个组，并且处理器以组中的完全连接方式彼此连接。当各个处理器彼此线性连接时，这些组彼此连接。

5. 发明授权

US08429664B2 Job scheduling apparatus and job scheduling method 有权
标题翻译：作业调度装置和作业调度方法
公开(公告)号：US08429664B2
公开(公告)日：2013-04-23
申请号：US12662940
申请日：2010-05-12
申请人： Yuichiro Ajima , Kouichi Kumon , Shinji Sumimoto
发明人： Yuichiro Ajima , Kouichi Kumon , Shinji Sumimoto
IPC分类号： G06F9/46
CPC分类号： G06F9/4881
摘要： When allocating an unallocated queued job, by using a CDA having a mesh structure to which active jobs are allocated, a job scheduling apparatus scans an event list that includes information about allocation events and release events for jobs, determines the coordinates and the time at which submeshes corresponding to the queued jobs are reserved, and arranges the submeshes by overlapping them on the CDA.
摘要翻译：当分配未分配的排队作业时，通过使用具有分配了活动作业的网格结构的CDA，作业调度装置扫描包括关于分配事件和释放事件的作业的信息的事件列表，确定坐标和时间保留与排队作业相对应的子网格，并通过将它们重叠在CDA上来排列子网。

6. 发明授权

US08204054B2 System having a plurality of nodes connected in multi-dimensional matrix, method of controlling system and apparatus 失效
标题翻译：具有以多维矩阵连接的多个节点的系统，控制系统和装置的方法
公开(公告)号：US08204054B2
公开(公告)日：2012-06-19
申请号：US12706137
申请日：2010-02-16
申请人： Yuichiro Ajima , Tomohiro Inoue , Shinya Hiramoto
发明人： Yuichiro Ajima , Tomohiro Inoue , Shinya Hiramoto
IPC分类号： H04L12/56
CPC分类号： G06F15/17368
摘要： A system has a plurality of nodes connected in a multi-dimensional matrix and having node addresses, respectively, each of the nodes having a processor, and a router for transmitting a request packet to a node adjacent to its own node located in n+1th dimension when the address of nth dimension of its own node is matched to the address of nth dimension of the target node, transmitting a response packet to a node adjacent to its own node located in nth dimension when the address of n+1th dimension of its own node is matched to the address of n+1th dimension of the response packet, wherein the router terminates a request packet when the address of the request packet is fully matched to the node address of its own node in all the dimensions, transfers the data conveyed by the request packet to the processor of its own node for processing.
摘要翻译：一种系统具有以多维矩阵连接并具有节点地址的多个节点，每个节点具有处理器，以及路由器，用于将请求分组发送到与其位于第n + 1个的其自身节点相邻的节点当其自身节点的第n维的地址与目标节点的第n维的地址匹配时，将其响应分组发送到邻近于其位于第n维的其自身节点的节点，当其第n维的第n维的地址自身节点与响应分组的n + 1维的地址相匹配，其中当请求分组的地址在所有维度上与其自身节点的节点地址完全匹配时，路由器终止请求分组，传送数据由请求包传送到其自身节点的处理器进行处理。

7. 发明授权

US09619300B2 Reduction operation device, a processor, and a computer system 有权
公开(公告)号：US09619300B2
公开(公告)日：2017-04-11
申请号：US13166114
申请日：2011-06-22
申请人： Shinya Hiramoto , Yuichiro Ajima , Tomohiro Inoue
发明人： Shinya Hiramoto , Yuichiro Ajima , Tomohiro Inoue
IPC分类号： G06F9/52 , G06F9/30
CPC分类号： G06F9/522 , G06F9/30
摘要： A reduction operation device detects a non-correspondence of an operation type or a data type in a reduction arithmetic operation of a parallel processing. The reduction operation device is inputted a plurality of the synchronization signals and data, sets each transmission destinations of the plurality of inputted synchronization signals and the plurality of data corresponding to a next stage of a reduction operation and executes the reduction operation. The synchronization unit in the reduction operation device detects the non-correspondence between the operation type or the data type included in an instruction of the reduction operation after the synchronization is established and controls the arithmetic operation of the arithmetic unit.

8. 发明申请

US20120250514A1 INFORMATION PROCESSING APPARATUS, PARALLEL COMPUTER SYSTEM, AND CONTROL METHOD OF PARALLEL COMPUTER SYSTEM 有权
标题翻译：信息处理装置，并行计算机系统和并行计算机系统的控制方法
公开(公告)号：US20120250514A1
公开(公告)日：2012-10-04
申请号：US13359635
申请日：2012-01-27
申请人： Shinya Hiramoto , Yuichiro Ajima , Tomohiro Inoue
发明人： Shinya Hiramoto , Yuichiro Ajima , Tomohiro Inoue
IPC分类号： H04L12/24
CPC分类号： H04L45/125 , H04L43/0882 , H04L45/121 , H04L45/127 , H04L45/70 , H04L47/115
摘要： An information processing apparatus connected to another information apparatus in a parallel computer system via a plurality of routes, includes: an arithmetic processing device to issue an instruction for collection of congestion information and for communication; a route information holding unit to hold route information for performing communication; a transmission unit to transmit a congestion information collection packet to any of the plurality of routes; a reception unit to receive a congestion information collection response packet corresponding to the congestion information collection packet from any of the plurality of routes; and a control unit to cause the transmission unit to transmit a congestion information collection packet, to select route information from the route information holding unit based on congestion information included in the congestion information collection response packet, and to cause the transmission unit to perform communication instructed by the arithmetic processing device based on the selected route information.
摘要翻译：一种信息处理装置，其通过多条路径与并行计算机系统中的另一信息装置连接，包括：发出用于收集拥塞信息和通信的指令的运算处理装置; 路由信息保持单元，保存用于进行通信的路由信息; 发送单元，向所述多个路由中的任一个发送拥塞信息收集分组; 接收单元，用于从所述多个路由中的任一个接收与所述拥塞信息收集分组相对应的拥塞信息收集响应分组; 以及控制单元，用于使所述发送单元发送拥塞信息收集包，基于所述拥挤信息收集响应包中包含的拥塞信息，从所述路径信息保持单元选择路由信息，并使所述发送单元进行通信指示由算术处理装置基于所选择的路线信息。

9. 发明申请

US20120159121A1 PARALLEL COMPUTER SYSTEM, SYNCHRONIZATION APPARATUS, AND CONTROL METHOD FOR THE PARALLEL COMPUTER SYSTEM 有权
标题翻译：并行计算机系统，同步计算机系统和并行计算机系统的控制方法
公开(公告)号：US20120159121A1
公开(公告)日：2012-06-21
申请号：US13323936
申请日：2011-12-13
申请人： Tomohiro INOUE , Yuichiro Ajima , Shinya Hiramoto
发明人： Tomohiro INOUE , Yuichiro Ajima , Shinya Hiramoto
IPC分类号： G06F15/76 , G06F9/06
CPC分类号： G06F15/17325
摘要： A synchronization apparatus includes a receiver that receives data from a synchronization apparatus of another node that performs synchronization with its own node from among the plurality of synchronization apparatuses and extracts synchronization information from the received data, a transmitter that transmits the data to the synchronization apparatus of the other node, a receiving state register that stores the extracted synchronization information, a delay unit that delays the received data by a specified period of time, and a controller that stores the extracted synchronization information and synchronization information from its own controller in the reception state register and causes the transmitter to transmit the data to the other node and returns the data to its own node back to its own controller via the delay unit when the extracted synchronization information and the synchronization information from its own controller are stored in the reception state register.
摘要翻译：同步装置包括从多个同步装置中与其自身节点进行同步的另一节点的同步装置接收数据的接收机，从接收到的数据中提取同步信息的发送机，发送数据到同步装置的同步装置另一个节点，存储所提取的同步信息的接收状态寄存器，将接收到的数据延迟指定时间段的延迟单元，以及将来自其自身的控制器的所提取的同步信息和同步信息存储在接收状态的控制器注册并使得发送器将数据发送到另一个节点，并且当提取的同步信息和来自其自己的控制器的同步信息被存储在接收状态寄存器中时，经由延迟单元将数据返回到其自己的节点返回到其自己的控制器。

10. 发明申请

US20110213946A1 PARALLEL COMPUTING SYSTEM AND COMMUNICATION CONTROL PROGRAM 审中-公开
标题翻译：并行计算系统和通信控制程序
公开(公告)号：US20110213946A1
公开(公告)日：2011-09-01
申请号：US12872338
申请日：2010-08-31
申请人： Yuichiro Ajima , Toshiyuki Shimizu , Hiroaki Ishihata
发明人： Yuichiro Ajima , Toshiyuki Shimizu , Hiroaki Ishihata
IPC分类号： G06F15/80 , G06F9/02
CPC分类号： G06F15/803
摘要： A parallel computing system includes a plurality of processors multi-dimensionally commented by an interconnection network, wherein each of the processors in the parallel computing system determines, in dimensional order, communication channels to other processors in the interconnection network, each of the processors sets, as relative coordinates of destination processors with respect to the plurality of processors in data communications performed at a same timing, relative coordinates common to all of the processors, and each of the processors performs data communications with destination processors having the set relative coordinates.
摘要翻译：并行计算系统包括由互连网络多维注释的多个处理器，其中并行计算系统中的每个处理器以尺寸顺序确定到互连网络中的其他处理器的通信信道，每个处理器集合，作为在相同定时执行的数据通信中的目标处理器相对于多个处理器的相对坐标，所有处理器共同的相对坐标，并且每个处理器执行与具有设定的相对坐标的目标处理器的数据通信。

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