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    • 1. 发明申请
    • DRIVING SYSTEM OF DISPLAY PANEL AND DRIVING METHOD THEREOF
    • 显示面板的驱动系统及其驱动方法
    • US20120299895A1
    • 2012-11-29
    • US13300175
    • 2011-11-18
    • Yu-Ting LINHung-Chun LiShin-Yuan PengChun-Chieh Wang
    • Yu-Ting LINHung-Chun LiShin-Yuan PengChun-Chieh Wang
    • G09G5/00
    • G09G3/3655G09G2300/043G09G2320/0214
    • A driving system of a display panel and a driving method thereof are provided, in which the display panel includes a plurality of pixel units, and the driving system includes a timing controller and a voltage generator. The timing controller is used for detecting data values of the pixel units, and calculating difference values between the data values of every two pixel units, in which the calculated pixel units are in successive rows. The timing controller obtains an aggregation value of absolute values of the difference values, and then provides a related control signal to the voltage generator according to whether the aggregation value reaches a threshold value. The voltage generator provides a common voltage or provides a compensation voltage to a common electrode according to content of the control signal.
    • 提供了显示面板的驱动系统及其驱动方法,其中显示面板包括多个像素单元,并且驱动系统包括定时控制器和电压发生器。 定时控制器用于检测像素单元的数据值,并且计算每两个像素单元的数据值之间的差值,其中所计算的像素单元是连续的行。 定时控制器获得差值的绝对值的聚合值,然后根据聚合值是否达到阈值,向电压发生器提供相关的控制信号。 电压发生器提供公共电压或根据控制信号的内容向公共电极提供补偿电压。
    • 3. 发明授权
    • Display device capable of switching gate high voltage
    • 能够切换门极高电压的显示装置
    • US08704815B2
    • 2014-04-22
    • US13158481
    • 2011-06-13
    • Hung-Chun LiChun-Chieh WangTung-Hsin Lan
    • Hung-Chun LiChun-Chieh WangTung-Hsin Lan
    • G09G3/36
    • G09G3/3696G09G3/3677G09G2300/0408G09G2320/041
    • A display device including a first voltage generator, a second voltage generator, a timing controller, a level shifter and a display panel is provided. The first voltage generator is configured to generate a gate high voltage. During a first period, the gate high voltage is a first voltage. After the first period, the gate high voltage is a second voltage. The first voltage is higher than the second voltage. The second voltage generator is configured to generate a gate low voltage. According to the gate high voltage and the gate low voltage, the level shifter shifts the voltage levels of the start signal, the clock signal and the inverse signal produced by the timing controller for driving a plurality of shift registers disposed on a substrate of the display panel. The shift registers is configured to output scanning signals in sequence.
    • 提供了包括第一电压发生器,第二电压发生器,定时控制器,电平转换器和显示面板的显示装置。 第一电压发生器被配置为产生栅极高压。 在第一时段期间,栅极高电压是第一电压。 第一个周期后,栅极高电压是第二个电压。 第一电压高于第二电压。 第二电压发生器被配置为产生栅极低电压。 根据栅极高电压和栅极低电压,电平移位器移位由定时控制器产生的起始信号,时钟信号和反向信号的电压电平,用于驱动布置在显示器的基板上的多个移位寄存器 面板。 移位寄存器被配置为依次输出扫描信号。
    • 4. 发明申请
    • DISPLAY DEVICE AND DRIVING METHOD THEREOF
    • 显示装置及其驱动方法
    • US20120105411A1
    • 2012-05-03
    • US13158481
    • 2011-06-13
    • Hung-Chun LiChun-Chieh WangTung-Hsin Lan
    • Hung-Chun LiChun-Chieh WangTung-Hsin Lan
    • G09G5/00
    • G09G3/3696G09G3/3677G09G2300/0408G09G2320/041
    • A display device including a first voltage generator, a second voltage generator, a timing controller, a level shifter and a display panel is provided. The first voltage generator is configured to generate a gate high voltage. During a first period, the gate high voltage is a first voltage. After the first period, the gate high voltage is a second voltage. The first voltage is higher than the second voltage. The second voltage generator is configured to generate a gate low voltage. According to the gate high voltage and the gate low voltage, the level shifter shifts the voltage levels of the start signal, the clock signal and the inverse signal produced by the timing controller for driving a plurality of shift registers disposed on a substrate of the display panel. The shift registers is configured to output scanning signals in sequence.
    • 提供了包括第一电压发生器,第二电压发生器,定时控制器,电平转换器和显示面板的显示装置。 第一电压发生器被配置为产生栅极高电压。 在第一时段期间,栅极高电压是第一电压。 第一个周期后,栅极高电压是第二个电压。 第一电压高于第二电压。 第二电压发生器被配置为产生栅极低电压。 根据栅极高电压和栅极低电压,电平移位器移位由定时控制器产生的起始信号,时钟信号和反向信号的电压电平,用于驱动布置在显示器的基板上的多个移位寄存器 面板。 移位寄存器被配置为依次输出扫描信号。
    • 5. 发明授权
    • Circuit design systems for replacing flip-flops with pulsed latches
    • 用脉冲锁存器代替触发器的电路设计系统
    • US08656324B2
    • 2014-02-18
    • US13310771
    • 2011-12-04
    • Hung-Chun LiMing-Chyuan ChenKunMing Ho
    • Hung-Chun LiMing-Chyuan ChenKunMing Ho
    • G06F17/50
    • G06F17/5045G06F17/505H03K3/012H03K3/356156
    • A circuit design system, methodology, and software are disclosed for generating circuit capable of consuming less dynamic power. In particular, the circuit design methodology entails modifying an initial circuit design including a clock network coupled to a plurality of edge-triggered flip-flops to generate a modified circuit design that uses pulsed latches driven by pulse generators in place of at least some of the flip-flops. Since pulsed latches use less dynamic power than edge-triggered flip-flops, the modified circuit may consume less dynamic power. The circuit design methodology may further entail adding delay cells for balancing the clock network to compensate for timing effects caused by the insertion of pulse generators. Additionally, the methodology may further include cloning of forbidden clock paths to make more flip-flops eligible for pulsed latch replacement.
    • 公开了用于产生能够消耗较少动态功率的电路的电路设计系统,方法和软件。 特别地,电路设计方法需要修改初始电路设计,包括耦合到多个边沿触发的触发器的时钟网络,以产生使用由脉冲发生器驱动的脉冲锁存器代替至少一些 人字拖。 由于脉冲锁存器比边沿触发的触发器使用更少的动态功率,所以修改的电路可能消耗较少的动态功率。 电路设计方法还可能需要添加用于平衡时钟网络的延迟单元以补偿由插入脉冲发生器引起的定时效应。 此外,该方法还可以包括克隆禁止的时钟路径以使更多触发器符合脉冲锁存器替换的条件。
    • 6. 发明申请
    • CIRCUIT DESIGN SYSTEMS FOR REPLACING FLIP-FLOPS WITH PULSED LATCHES
    • 用于更换带有脉冲锁存器的浮标的电路设计系统
    • US20120079437A1
    • 2012-03-29
    • US13310771
    • 2011-12-04
    • Hung-Chun LiMing-Chyuan ChenKunMing Ho
    • Hung-Chun LiMing-Chyuan ChenKunMing Ho
    • G06F17/50
    • G06F17/5045G06F17/505H03K3/012H03K3/356156
    • A circuit design system, methodology, and software are disclosed for generating circuit capable of consuming less dynamic power. In particular, the circuit design methodology entails modifying an initial circuit design including a clock network coupled to a plurality of edge-triggered flip-flops to generate a modified circuit design that uses pulsed latches driven by pulse generators in place of at least some of the flip-flops. Since pulsed latches use less dynamic power than edge-triggered flip-flops, the modified circuit may consume less dynamic power. The circuit design methodology may further entail adding delay cells for balancing the clock network to compensate for timing effects caused by the insertion of pulse generators. Additionally, the methodology may further include cloning of forbidden clock paths to make more flip-flops eligible for pulsed latch replacement.
    • 公开了用于产生能够消耗较少动态功率的电路的电路设计系统,方法和软件。 特别地,电路设计方法需要修改初始电路设计,包括耦合到多个边沿触发的触发器的时钟网络,以产生使用由脉冲发生器驱动的脉冲锁存器代替至少一些 人字拖。 由于脉冲锁存器比边沿触发的触发器使用更少的动态功率,所以修改的电路可能消耗较少的动态功率。 电路设计方法还可能需要添加用于平衡时钟网络的延迟单元以补偿由插入脉冲发生器引起的定时效应。 此外,该方法还可以包括克隆禁止的时钟路径以使更多触发器符合脉冲锁存器替换的条件。
    • 7. 发明授权
    • System and method of replacing flip-flops with pulsed latches in circuit designs
    • 在电路设计中用脉冲锁存器代替触发器的系统和方法
    • US07694242B1
    • 2010-04-06
    • US11609304
    • 2006-12-11
    • Hung-Chun LiMing-Chyuan ChenKunMing Ho
    • Hung-Chun LiMing-Chyuan ChenKunMing Ho
    • G06F17/50
    • G06F17/5045G06F17/505H03K3/012H03K3/356156
    • A circuit design system, methodology, and software are disclosed for generating circuit capable of consuming less dynamic power. In particular, the circuit design methodology entails modifying an initial circuit design including a clock network coupled to a plurality of edge-triggered flip-flops to generate a modified circuit design that uses pulsed latches driven by pulse generators in place of at least some of the flip-flops. Since pulsed latches use less dynamic power than edge-triggered flip-flops, the modified circuit may consume less dynamic power. The circuit design methodology may further entail adding delay cells for balancing the clock network to compensate for timing effects caused by the insertion of pulse generators. Additionally, the methodology may further include cloning of forbidden clock paths to make more flip-flops eligible for pulsed latch replacement.
    • 公开了用于产生能够消耗较少动态功率的电路的电路设计系统,方法和软件。 特别地,电路设计方法需要修改初始电路设计,包括耦合到多个边沿触发的触发器的时钟网络,以产生使用由脉冲发生器驱动的脉冲锁存器代替至少一些 人字拖。 由于脉冲锁存器比边沿触发的触发器使用更少的动态功率,所以修改的电路可能消耗较少的动态功率。 电路设计方法还可能需要添加用于平衡时钟网络的延迟单元以补偿由插入脉冲发生器引起的定时效应。 此外,该方法还可以包括克隆禁止的时钟路径以使更多触发器符合脉冲锁存器替换的条件。
    • 8. 发明授权
    • Method and apparatus for over-driving liquid crystal display
    • 用于过驱动液晶显示器的方法和装置
    • US08344979B2
    • 2013-01-01
    • US12638406
    • 2009-12-15
    • Mu-Shan LiaoTung-Hsin LanHung-Chun Li
    • Mu-Shan LiaoTung-Hsin LanHung-Chun Li
    • G09G3/36G09G5/10
    • G09G5/395G09G3/003G09G3/3648G09G2320/0252G09G2320/0271G09G2320/0673
    • A method and an apparatus for over-driving a liquid crystal display (LCD) are provided, which are suitable for compensating a gray level brightness of the LCD. The method includes the following steps. Firstly, a data buffer unit outputs a current frame data. Then, the current frame data is stored into a frame memory unit, and the frame memory unit outputs a previous frame data. Next, several look-up tables (LUTs) are searched for a driving voltage in a corresponding LUT according to the current frame data and the previous frame data. Afterward, a position scanning unit receives the current frame data to determine a current position. Finally, a multiplexer outputs the corresponding driving voltage at the current position. Thus, a display panel has the same gray level brightness in upper, middle, and lower portions thereof, thereby avoiding ghosting.
    • 提供一种用于过驱动液晶显示器(LCD)的方法和装置,其适用于补偿LCD的灰度级亮度。 该方法包括以下步骤。 首先,数据缓冲器单元输出当前帧数据。 然后,将当前帧数据存储到帧存储器单元中,并且帧存储器单元输出先前的帧数据。 接下来,根据当前帧数据和先前帧数据,搜索相应LUT中的驱动电压的几个查找表(LUT)。 之后,位置扫描单元接收当前帧数据以确定当前位置。 最后,多路复用器在当前位置输出相应的驱动电压。 因此,显示面板的上部,中部和下部具有相同的灰度级亮度,从而避免重影。