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1. 发明申请

US20080092088A1 Process monitoring system and method 有权
标题翻译：过程监控系统和方法
公开(公告)号：US20080092088A1
公开(公告)日：2008-04-17
申请号：US10817104
申请日：2004-04-01
申请人： Youval Nehmadi , Zamir Abraham , Gil Sod-Moriah , Yair Eran , Chen Ofek , Yaron Cohen , Ariel Ben-Porath
发明人： Youval Nehmadi , Zamir Abraham , Gil Sod-Moriah , Yair Eran , Chen Ofek , Yaron Cohen , Ariel Ben-Porath
IPC分类号： G06F17/50
CPC分类号： G01R31/303 , G01N23/225 , H01J2237/2814
摘要： The invention provides a method that includes the stages of: (i) receiving design information representative of a portion of an object that includes sub micron measurement targets, (ii) processing the received design information to provide a large number of measurement targets; and (iii) associating target measurement parameters to each of large number of measurement targets.The invention provides a system that includes: (i) an interface for receiving design information representative of a portion of a layer of an object that includes sub micron measurement targets; and (ii) a processor, coupled to the interface, for processing the received design information to provide a large number of measurement targets; and for associating target measurement parameters to each of large number of measurement targets.
摘要翻译：本发明提供了一种方法，其包括以下阶段：（i）接收表示包含亚微米测量目标的对象的一部分的设计信息，（ii）处理所接收的设计信息以提供大量的测量目标; 和（iii）将目标测量参数与大量测量目标中的每一个相关联。本发明提供了一种系统，其包括：（i）接口，用于接收表示包含亚微米测量目标的物体层的一部分的设计信息; 以及（ii）耦合到所述接口的处理器，用于处理所接收的设计信息以提供大量的测量目标; 并且用于将目标测量参数与大量测量目标中的每一个相关联。

2. 发明授权

US07587700B2 Process monitoring system and method for processing a large number of sub-micron measurement targets 有权
标题翻译：用于处理大量亚微米测量目标的过程监控系统和方法
公开(公告)号：US07587700B2
公开(公告)日：2009-09-08
申请号：US10817104
申请日：2004-04-01
申请人： Youval Nehmadi , Zamir Abraham , Gil Sod-Moriah , Yair Eran , Chen Ofek , Yaron Cohen , Ariel Ben-Porath
发明人： Youval Nehmadi , Zamir Abraham , Gil Sod-Moriah , Yair Eran , Chen Ofek , Yaron Cohen , Ariel Ben-Porath
IPC分类号： G06F17/50
CPC分类号： G01R31/303 , G01N23/225 , H01J2237/2814
摘要： The invention provides a method that includes the stages of: (i) receiving design information representative of a portion of an object that includes sub micron measurement targets, (ii) processing the received design information to provide a large number of measurement targets; and (iii) associating target measurement parameters to each of large number of measurement targets.The invention provides a system that includes: (i) an interface for receiving design information representative of a portion of a layer of an object that includes sub micron measurement targets; and (ii) a processor, coupled to the interface, for processing the received design information to provide a large number of measurement targets; and for associating target measurement parameters to each of large number of measurement targets.
摘要翻译：本发明提供了一种方法，其包括以下阶段：（i）接收表示包含亚微米测量目标的对象的一部分的设计信息，（ii）处理所接收的设计信息以提供大量的测量目标; 和（iii）将目标测量参数与大量测量目标中的每一个相关联。本发明提供了一种系统，其包括：（i）接口，用于接收表示包含亚微米测量目标的物体层的一部分的设计信息; 以及（ii）耦合到所述接口的处理器，用于处理所接收的设计信息以提供大量的测量目标; 并且用于将目标测量参数与大量测量目标中的每一个相关联。

3. 发明授权

US07135344B2 Design-based monitoring 有权
标题翻译：基于设计的监控
公开(公告)号：US07135344B2
公开(公告)日：2006-11-14
申请号：US10780377
申请日：2004-02-17
申请人： Youval Nehmadi , Josephine Phua , Jacob Joseph Orbon, Jr. , Ariel Ben-Porath , Evgeny Levin , Ofer Bokobza
发明人： Youval Nehmadi , Josephine Phua , Jacob Joseph Orbon, Jr. , Ariel Ben-Porath , Evgeny Levin , Ofer Bokobza
IPC分类号： H01L21/66
CPC分类号： G03F1/84 , G03F1/36
摘要： A method for monitoring fabrication of an integrated circuit (IC) on a semiconductor wafer includes generating a product design profile (PDP) using an electronic design automation (EDA) tool, the PDP comprising an indication of a site in at least one layer of the IC that is susceptible to a process fault. Upon fabricating at least one layer of the IC on the wafer, a process monitoring tool is applied to perform a measurement at the site in at least one layer responsively to the PDP.
摘要翻译：一种用于监测半导体晶片上的集成电路（IC）的制造的方法包括使用电子设计自动化（EDA）工具生成产品设计简档（PDP），所述PDP包括至少一层中的位置的指示易受过程故障影响的IC。在晶片上制造至少一层IC时，应用过程监控工具，以响应于PDP在至少一层中在现场进行测量。

4. 发明申请

US20090007030A1 DESIGN-BASED MONITORING 审中-公开
标题翻译：基于设计的监控
公开(公告)号：US20090007030A1
公开(公告)日：2009-01-01
申请号：US11538387
申请日：2006-10-03
申请人： Youval Nehmadi , Josephine Phua , Jacob Joseph Orbon, JR. , Ariel Ben-Porath , Evgeny Levin , Ofer Bokobza
发明人： Youval Nehmadi , Josephine Phua , Jacob Joseph Orbon, JR. , Ariel Ben-Porath , Evgeny Levin , Ofer Bokobza
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G03F1/84 , G03F1/36
摘要： A method for monitoring fabrication of an integrated circuit (IC) on a semiconductor wafer includes generating a product design profile (PDP) using an electronic design automation (EDA) tool, the PDP comprising an indication of a site in a layer of the IC that is susceptible to a process fault. Upon fabricating the layer of the IC on the wafer, a process monitoring tool is applied to perform a measurement at the site in the layer responsively to the PDP.
摘要翻译：一种用于监控半导体晶片上的集成电路（IC）的制造的方法，包括使用电子设计自动化（EDA）工具生成产品设计简档（PDP），所述PDP包括IC层中的位置的指示，容易受到过程故障的影响。在晶片上制造IC层时，应用过程监控工具，以响应于PDP在层中的位置进行测量。

5. 发明申请

US20070052963A1 GROUPING SYSTEMATIC DEFECTS WITH FEEDBACK FROM ELECTRICAL INSPECTION 有权
标题翻译：用电气检查反馈组合系统缺陷
公开(公告)号：US20070052963A1
公开(公告)日：2007-03-08
申请号：US11553745
申请日：2006-10-27
申请人： JACOB ORBON , Youval Nehmadi , Ofer Bokobza , Ariel Ben-Porath , Erez Ravid , Rinat Shimshi , Vicky Svidenko
发明人： JACOB ORBON , Youval Nehmadi , Ofer Bokobza , Ariel Ben-Porath , Erez Ravid , Rinat Shimshi , Vicky Svidenko
IPC分类号： G01N21/84
CPC分类号： G03F7/7065 , G03F1/84
摘要： Methods and apparatus for categorizing defects on workpieces, such as semiconductor wafers and masks used in lithographically writing patterns into such wafers are provided. For some embodiments, by analyzing the layout in the neighborhood of the defect, and matching it to similar defected neighborhoods in different locations across the die, defects may be categorized by common structures in which they occur.
摘要翻译：提供了用于将工件上的缺陷（例如半导体晶片和用于将这种晶片刻画图案所用的掩模）分类的方法和装置。对于一些实施例，通过分析缺陷附近的布局，并且将其匹配到跨越裸片的不同位置中的类似的缺陷邻域，可以通过它们出现的共同结构对缺陷进行分类。

6. 发明申请

US20060269120A1 DESIGN-BASED METHOD FOR GROUPING SYSTEMATIC DEFECTS IN LITHOGRAPHY PATTERN WRITING SYSTEM 有权
标题翻译：基于设计的方法，用于分类刻画图案系统中的系统缺陷
公开(公告)号：US20060269120A1
公开(公告)日：2006-11-30
申请号：US11383395
申请日：2006-05-15
申请人： YOUVAL NEHMADI , Ofer Bokobza , Ariel Ben-Porath , Erez Ravid , Rinat Shimsht , Vicky Svidenko , Gilad Almogy
发明人： YOUVAL NEHMADI , Ofer Bokobza , Ariel Ben-Porath , Erez Ravid , Rinat Shimsht , Vicky Svidenko , Gilad Almogy
IPC分类号： G06K9/00
CPC分类号： G03F7/7065 , G03F1/84
摘要： Methods and apparatus for categorizing defects on workpieces, such as semiconductor wafers and masks used in lithographically writing patterns into such wafers are provided. For some embodiments, by analyzing the layout in the neighborhood of the defect, and matching it to similar defected neighborhoods in different locations across the die, defects may be categorized by common structures in which they occur.
摘要翻译：提供了用于将工件上的缺陷（例如半导体晶片和用于将这种晶片刻画图案所用的掩模）分类的方法和装置。对于一些实施例，通过分析缺陷附近的布局，并且将其匹配到跨越裸片的不同位置中的类似的缺陷邻域，可以通过它们出现的共同结构对缺陷进行分类。

7. 发明申请

US20050010890A1 Design-based monitoring 有权
标题翻译：基于设计的监控
公开(公告)号：US20050010890A1
公开(公告)日：2005-01-13
申请号：US10780377
申请日：2004-02-17
申请人： Youval Nehmadi , Josephine Phua , Jacob Orbon , Ariel Ben-Porath , Evgeny Levin , Ofer Bokobza
发明人： Youval Nehmadi , Josephine Phua , Jacob Orbon , Ariel Ben-Porath , Evgeny Levin , Ofer Bokobza
IPC分类号： G03F1/00 , G03F1/14 , G06F17/50
CPC分类号： G03F1/84 , G03F1/36
摘要： A method for monitoring fabrication of an integrated circuit (IC) on a semiconductor wafer includes generating a product design profile (PDP) using an electronic design automation (EDA) tool, the PDP comprising an indication of a site in at least one layer of the IC that is susceptible to a process fault. Upon fabricating at least one layer of the IC on the wafer, a process monitoring tool is applied to perform a measurement at the site in at least one layer responsively to the PDP.
摘要翻译：一种用于监测半导体晶片上的集成电路（IC）的制造的方法包括使用电子设计自动化（EDA）工具生成产品设计简档（PDP），所述PDP包括至少一层中的位置的指示易受过程故障影响的IC。在晶片上制造至少一层IC时，应用过程监控工具，以响应于PDP在至少一层中在现场进行测量。

8. 发明授权

US07760929B2 Grouping systematic defects with feedback from electrical inspection 有权
标题翻译：将系统缺陷与电气检查反馈分组
公开(公告)号：US07760929B2
公开(公告)日：2010-07-20
申请号：US11553745
申请日：2006-10-27
申请人： Jacob J. Orbon , Youval Nehmadi , Ofer Bokobza , Ariel Ben-Porath , Erez Ravid , Rinat Shimshi , Vicky Svidenko
发明人： Jacob J. Orbon , Youval Nehmadi , Ofer Bokobza , Ariel Ben-Porath , Erez Ravid , Rinat Shimshi , Vicky Svidenko
IPC分类号： G06K9/00
CPC分类号： G03F7/7065 , G03F1/84
摘要： Methods and apparatus for categorizing defects on workpieces, such as semiconductor wafers and masks used in lithographically writing patterns into such wafers are provided. For some embodiments, by analyzing the layout in the neighborhood of the defect, and matching it to similar defected neighborhoods in different locations across the die, defects may be categorized by common structures in which they occur.
摘要翻译：提供了用于将工件上的缺陷（例如半导体晶片和用于将这种晶片刻画图案所用的掩模）分类的方法和装置。对于一些实施例，通过分析缺陷附近的布局，并且将其匹配到跨越裸片的不同位置中的类似的缺陷邻域，可以通过它们出现的共同结构对缺陷进行分类。

9. 发明授权

US07760347B2 Design-based method for grouping systematic defects in lithography pattern writing system 有权
标题翻译：基于设计的光刻图案写入系统中系统缺陷分组的方法
公开(公告)号：US07760347B2
公开(公告)日：2010-07-20
申请号：US11383395
申请日：2006-05-15
申请人： Youval Nehmadi , Ofer Bokobza , Ariel Ben-Porath , Erez Ravid , Rinat Shishi , Vicky Svidenko , Gilad Almogy , Jacob J. Orbon, Jr.
发明人： Youval Nehmadi , Ofer Bokobza , Ariel Ben-Porath , Erez Ravid , Rinat Shishi , Vicky Svidenko , Gilad Almogy , Jacob J. Orbon, Jr.
IPC分类号： G01N21/00
CPC分类号： G03F7/7065 , G03F1/84
摘要： Methods and apparatus for categorizing defects on workpieces, such as semiconductor wafers and masks used in lithographically writing patterns into such wafers are provided. For some embodiments, by analyzing the layout in the neighborhood of the defect, and matching it to similar defected neighborhoods in different locations across the die, defects may be categorized by common structures in which they occur.
摘要翻译：提供了用于将工件上的缺陷（例如半导体晶片和用于将这种晶片刻画图案所用的掩模）分类的方法和装置。对于一些实施例，通过分析缺陷附近的布局，并且将其匹配到跨越裸片的不同位置中的类似的缺陷邻域，可以通过它们出现的共同结构对缺陷进行分类。

10. 发明授权

US07217579B2 Voltage contrast test structure 有权
标题翻译：电压对比度测试结构
公开(公告)号：US07217579B2
公开(公告)日：2007-05-15
申请号：US10327537
申请日：2002-12-19
申请人： Ariel Ben-Porath , Douglas Ray Hendricks
发明人： Ariel Ben-Porath , Douglas Ray Hendricks
IPC分类号： H01L21/00 , H01L21/66 , H01L23/58 , G01R33/02 , G01R31/26
CPC分类号： H01L22/34 , G01N23/2258
摘要： A method for electrically testing a semiconductor wafer during integrated-circuit fabrication process, the method including: (i) providing a scanning charged-particle microscope (SCPM), having a defined scanning plane and operative, while in any one mechanical state, to scan a surface in the scanning plane within a two-dimensional scanning window, which has a given maximum size; (ii) providing in association with any layer of the wafer, it being a test layer, one or more test structures, each test structure including normally conductive areas within a normally non-conductive background in one or more layers, which include said test layer, the conductive areas formed as one or more patterns; the patterns in said test layer include one or more clusters of mutually isolated pads; each pad is conductively connected with a corresponding distinct point on the patterns and all the pads in any one cluster are sized and arranged so that at least a significant portion of each pad falls within a common window whose size does not exceed said maximum size of said scanning window; (iii) with said test layer forming the top surface of the wafer, placing the wafer on the SCPM and adjusting the mechanical state of the SCPM so that at least a significant portion of each pad in any one of said clusters is within said scanning window; (iv) causing the SCPM, while in said mechanical state, to scan all of the pads of said one cluster and thereby to provide information about the electrical state of the respective test structure.
摘要翻译：一种用于在集成电路制造过程中对半导体晶片进行电测试的方法，所述方法包括：（i）提供具有限定的扫描平面并在任何一个机械状态下操作的扫描带电粒子显微镜（SCPM），以扫描在二维扫描窗口内的扫描平面中的表面，其具有给定的最大尺寸; （ii）提供与晶片的任何层相关联的，它是测试层，一个或多个测试结构，每个测试结构包括在一个或多个层中的正常非导电背景内的正常导电区域，其包括所述测试层形成为一个或多个图案的导电区域; 所述测试层中的图案包括一个或多个相互隔离的焊盘簇; 每个焊盘与图案上的相应的不同点导电连接，并且任何一个簇中的所有焊盘的尺寸和布置尺寸和布置成使得每个焊盘的至少一个重要部分落入公共窗口内，该窗口的尺寸不超过所述扫描窗口（iii）所述测试层形成晶片的顶表面，将晶片放置在SCPM上并调整SCPM的机械状态，使得任何一个所述簇中的每个焊盘的至少大部分在所述扫描窗口内 ; （iv）在所述机械状态下使所述SCPM扫描所述一个簇的所有垫，从而提供关于各个测试结构的电气状态的信息。

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