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1. 发明授权

US06878307B2 Low temperature firable PZT compositions and piezoelectric ceramic devices using the same 有权
标题翻译：低温可熔PZT组合物和使用其的压电陶瓷器件
公开(公告)号：US06878307B2
公开(公告)日：2005-04-12
申请号：US10195165
申请日：2002-07-16
申请人： Youri Ponomarev , Young Min Kim
发明人： Youri Ponomarev , Young Min Kim
IPC分类号： C04B35/493 , H01L41/083 , H01L41/107 , H01L41/187 , C04B35/491 , H01B1/00 , H01L41/04
CPC分类号： C04B35/6262 , B32B2311/08 , C04B35/493 , C04B35/63 , C04B35/6303 , C04B35/634 , C04B35/63416 , C04B2235/3203 , C04B2235/3206 , C04B2235/3213 , C04B2235/3215 , C04B2235/3267 , C04B2235/3284 , C04B2235/3298 , C04B2235/445 , C04B2235/5445 , C04B2235/6025 , C04B2235/656 , C04B2237/346 , C04B2237/348 , C04B2237/408 , H01L41/083 , H01L41/107 , H01L41/1876
摘要： A piezoelectric ceramic composition firable at a reduced sintering temperature is provided. The main composition is expressed with the general formula: [(Pb1-m-n-pSrmBanCdp)(ZrxTi1-x)1-k(BiaMnb)k]O3+yBi2O3+z(Fluorine Compound) where 0.00≦m
摘要翻译：提供了一种在降低的烧结温度下可预期的压电陶瓷组合物。主要成分用以下通式表示：其中0.00 <= m <0.15,0.00 <= n <0.15,0.00 <（m + n）<0.21,0.00

2. 发明申请

US20100010550A1 BRANCHING THERAPY ELEMENTS AND METHOD OF THEIR INSERTION INTO LIVING TISSUE 审中-公开
标题翻译：分配治疗单元及其入侵组织的方法
公开(公告)号：US20100010550A1
公开(公告)日：2010-01-14
申请号：US12442528
申请日：2007-09-20
申请人： Youri Ponomarev , Matthias Merz , Remco Henricus Wilhelmus Pijnenburg
发明人： Youri Ponomarev , Matthias Merz , Remco Henricus Wilhelmus Pijnenburg
IPC分类号： A61N1/05 , A61M31/00 , A61B19/00
CPC分类号： A61N1/0529 , A61N1/0534
摘要： An implantable medical system for electrical recording and or providing therapy to a plurality of tissue sites without damage to surrounding blood vessels is disclosed comprising: an implant body having a plurality of therapy elements, the elements being hingedly attached at one end to the surface of the body and releasably extendable outward from the surface of the body at the other end; a release mechanism for each of the elements; and a coating material covering the body and the elements; wherein upon dissolution of the coating material after implantation, the release mechanism is capable of causing the elements to extend outward at one end from the surface of the body and into a plurality of tissue sites without damage to the surrounding blood vessels. The method of implanting the system into a body is also disclosed.
摘要翻译：公开了一种用于对多个组织部位进行电记录和/或对周围血管的损伤提供治疗的可植入医疗系统，包括：具有多个治疗元件的植入体，所述元件在一端铰接附接到并且在另一端从主体的表面可释放地向外延伸; 用于每个元件的释放机构; 以及覆盖所述主体和所述元件的涂层材料; 其中，在植入后溶解涂层材料时，释放机构能够使元件在一端从身体的表面向外延伸并且进入多个组织部位而不损坏周围的血管。还公开了将系统植入体内的方法。

3. 发明授权

US07416957B2 Method for forming a strained Si-channel in a MOSFET structure 有权
标题翻译：在MOSFET结构中形成应变Si沟道的方法
公开(公告)号：US07416957B2
公开(公告)日：2008-08-26
申请号：US10596422
申请日：2004-11-30
申请人： Youri Ponomarev
发明人： Youri Ponomarev
IPC分类号： H01L21/30
CPC分类号： H01L21/02694 , H01L21/02381 , H01L21/0245 , H01L21/02502 , H01L21/02505 , H01L21/02532
摘要： Method for forming a strained Si layer on a substrate (1), including formation of: an epitaxial SiGe layer (4) on a Si surface, and of: the strained Si layer by epitaxial growth of the Si layer on top of the epitaxial SiGe layer (4), the Si layer being strained due to the epitaxial growth, wherein the substrate (1) is a Silicon-On-Insulator substrate with a support layer (1), a buried silicon dioxide layer (BOX) and a monocrystalline Si surface layer (3), the method further including: ion implantation of the Si surface layer (3) and the epitaxial SiGe layer (4) to transform the Si surface layer (3) into an amorphous Si layer (3B) and a portion of the epitaxial SiGe layer (4) into an amorphous SiGe layer (5), a further portion of the epitaxial SiGe layer (4) being a remaining monocrystalline SiGe layer (6), the amorphous Si layer (3B), the amorphous SiGe layer and the remaining monocrystalline SiGe layer (6) forming a layer stack (3B, 5, 6) on the buried silicon dioxide layer (BOX), with the amorphous Si layer (3B) being adjacent to the buried silicon dioxide layer (BOX).
摘要翻译：在基板（1）上形成应变Si层的方法，包括在Si表面上形成外延SiGe层（4），以及通过在外延SiGe顶部外延生长Si层的应变Si层层（4），由于外延生长，Si层被应变，其中衬底（1）是具有支撑层（1），掩埋二氧化硅层（BOX）和单晶Si（Si）的硅绝缘体衬底表面层（3），所述方法还包括：Si表面层（3）和外延SiGe层（4）的离子注入，以将Si表面层（3）转变为非晶Si层（3B）和部分的外延SiGe层（4）的非晶SiGe层（5）中的另一部分外延SiGe层（4）是剩余的单晶SiGe层（6），非晶Si层（3B），非晶SiGe 层和剩余的单晶SiGe层（6）在墓碑上形成层叠（3 B，5,6）二氧化硅层（BOX），其中非晶Si层（3B）与掩埋二氧化硅层（BOX）相邻。

4. 发明申请

US20080093668A1 Method for the Manufacture of a Semiconductor Device and a Semiconductor Device Obtained Through It 有权
标题翻译：用于制造半导体器件的方法和通过它获得的半导体器件
公开(公告)号：US20080093668A1
公开(公告)日：2008-04-24
申请号：US11722988
申请日：2005-12-19
申请人： Youri Ponomarev , Josine Loo
发明人： Youri Ponomarev , Josine Loo
IPC分类号： H01L29/786 , H01L21/84
CPC分类号： H01L29/66772 , H01L29/78648
摘要： The invention relates to a semiconductor device (10) having a semiconductor body (2), comprising a field effect transistor, a first gate dielectric (6A) being formed on a first surface at the location of the channel region (5) and on it a first gate electrode (7), a sunken ion implantation (20) being executed from the first side of the semiconductor body (2) through and on both sides of the first gate electrode (7), which implantation results in a change of property of the silicon below the first gate electrode (7) compared to the silicon on both sides of the gate electrode (7) in a section of the channel region (5) remote from the first gate dielectric (6A), and on the second surface of the semiconductor body (2) a cavity (30) being provided therein by means of selective etching while use is made of the change of property of the silicon. A second gate (6B,8) is deposited in the cavity thus formed. Before the ion implantation (20), a mask (M1) is formed on both sides of the gate electrode (7) and at a distance thereof, whereby after the ion implantation (20) at the location of the mask (M1) also a change in property of the silicon is obtained. In this way the device (10) can be easily provided with lateral insulation regions. Also the end regions of the gate electrodes (7,8) can in this way be surrounded by insulation regions.
摘要翻译：本发明涉及具有半导体本体（2）的半导体器件（10），包括场效应晶体管，第一栅极电介质（6A）形成在沟道区域（5）的位置处的第一表面上，它是第一栅电极（7），从半导体本体（2）的第一侧通过第一栅电极（7）的两侧执行沉没离子注入（20），该注入导致与第一栅极电极（7）下方的硅的特性相比，在远离第一栅极电介质（6A）的沟道区域（5）的部分中与栅电极（7）的两侧的硅相比，半导体主体（2）的第二表面通过选择性蚀刻在其中提供空腔（30），同时使用硅的性质变化。第二栅极（6B，8）沉积在如此形成的空腔中。在离子注入（20）之前，在栅电极（7）的两侧和其一定距离处形成掩模（M 1），由此在掩模（M1）的位置处的离子注入（20）之后，也获得了硅的性质变化。以这种方式，设备（10）可以容易地设置有侧向绝缘区域。此外，栅电极（7,8）的端部区域也可以这样被绝缘区域包围。

5. 发明授权

US06544851B2 Method of manufacturing a semiconductor device having a pocket implant in channel region 有权
标题翻译：制造在通道区域具有口袋植入物的半导体器件的方法
公开(公告)号：US06544851B2
公开(公告)日：2003-04-08
申请号：US09784421
申请日：2001-02-15
申请人： Youri Ponomarev , Marian Nelia Webster , Charles Johan Joachim Dachs
发明人： Youri Ponomarev , Marian Nelia Webster , Charles Johan Joachim Dachs
IPC分类号： H01L21336
CPC分类号： H01L29/66492 , H01L21/823842 , H01L29/1045 , H01L29/1083 , H01L29/66545 , H01L29/6659
摘要： In a method of manufacturing a semiconductor device comprising a semiconductor body (1) of a first conductivity type which is provided at a surface (2) with a transistor having a gate (28) insulated from a channel (13) provided at the surface (2) of the semiconductor body (1) by a gate dielectric (26), a structure is provided on the surface (2) comprising a dielectric layer (14) having a recess (16), which recess (16) is aligned to a source zone (11,9) and a drain zone (12,9) of a second conductivity type provided at the surface (2) of the semiconductor body (1) and has side walls (17) extending substantially perpendicularly to the surface (2) of the semiconductor body (1). In this recess (16), a double-layer (20) is applied consisting of a second sub-layer (19) on top of a first sub-layer (18), which second sub-layer (19) is removed over part of its thickness until the first sub-layer is exposed, which first sub-layer (18) is selectively etched with respect to the second sub-layer (19) and the side walls (17) of the recess (16) to a depth, thereby forming trenches (21) extending substantially perpendicularly to the surface (2) of the semiconductor body (1). Via these trenches (21) impurities of the first conductivity type are introduced into the semiconductor body (1), thereby forming pocket implants (22).
摘要翻译：在制造半导体器件的方法中，所述半导体器件包括第一导电类型的半导体本体（1），所述半导体本体（1）设置在具有与设置在所述表面处的沟道（13）绝缘的具有栅极（28）的晶体管的表面（2）通过栅极电介质（26）将半导体本体（1）的结构（2）设置在包括具有凹部（16）的电介质层（14）的表面（2）上的结构，该凹部（16）与源区（11,9）和设置在半导体本体（1）的表面（2）处的第二导电类型的漏区（12,9），并且具有基本上垂直于表面（2）延伸的侧壁）半导体本体（1）。在该凹部（16）中，由在第一子层（18）的顶部上的第二子层（19）构成的双层（20），该第二子层（19）在部分其厚度直到第一子层露出为止，将第一子层（18）相对于第二子层（19）和凹部（16）的侧壁（17）选择性地蚀刻到深度从而形成基本上垂直于半导体本体（1）的表面（2）延伸的沟槽（21）。通过这些沟槽（21）将第一导电类型的杂质引入半导体本体（1）中，从而形成袋状植入物（22）。

6. 发明申请

US20110301903A1 SENSOR CALIBRATION IN AN RFID TAG 审中-公开
标题翻译： RFID标签中的传感器校准
公开(公告)号：US20110301903A1
公开(公告)日：2011-12-08
申请号：US12992824
申请日：2009-04-30
申请人： Arelie Humbert , Gilbert Curatola , Matthias Merz , Remco Henricus Wilhelmus Pijenburg , Romano Hoofman , Youri Ponomarev
发明人： Arelie Humbert , Gilbert Curatola , Matthias Merz , Remco Henricus Wilhelmus Pijenburg , Romano Hoofman , Youri Ponomarev
IPC分类号： G01D18/00
CPC分类号： G01D18/008 , G01K1/024 , G01K3/04 , G01K15/00
摘要： A sensor, electrically connected to transponder, is calibrated in an environment of operational use of the transponder. The calibrating uses as a reference a value of a parameter representative of the environment.
摘要翻译：电连接到应答器的传感器在应答器的操作使用环境中被校准。校准使用代表环境的参数的值作为参考。

7. 发明授权

US07951684B2 Semiconductor device method of manfacturing a quantum well structure and a semiconductor device comprising such a quantum well structure 有权
标题翻译：制造量子阱结构的半导体器件方法和包括这种量子阱结构的半导体器件
公开(公告)号：US07951684B2
公开(公告)日：2011-05-31
申请号：US12429348
申请日：2009-04-24
申请人： Youri Ponomarev
发明人： Youri Ponomarev
IPC分类号： H01L21/76
CPC分类号： H01L29/78696 , H01L29/1054 , H01L29/152 , H01L29/7782 , H01L29/7838 , H01L29/78687 , Y10S438/962
摘要： A semiconductor device (1) and a method are disclosed for obtaining on a substrate (2) a multilayer structure (3) with a quantum well structure (4). The quantum well structure (4) comprises a semiconductor layer (5) sandwiched by insulating layers (6,6′), wherein the material of the insulating layers (6,6′) has preferably a high dielectric constant. In a FET the quantum wells (4,9) function as channels, allowing a higher drive current and a lower off current. Short channel effects are reduced. The multi-channel FET is suitable to operate even for sub-35 nm gate lengths.In the method the quantum wells are formed by epitaxial growth of the high dielectric constant material and the semiconductor material alternately on top of each other, preferably with MBE.
摘要翻译：公开了一种用于在基板（2）上获得具有量子阱结构（4）的多层结构（3）的半导体器件（1）和方法。量子阱结构（4）包括被绝缘层（6,6'）夹持的半导体层（5），其中绝缘层（6,6'）的材料优选具有高的介电常数。在FET中，量子阱（4,9）用作通道，允许更高的驱动电流和更低的截止电流。短信道效应降低。多通道FET适用于甚至对于35nm以下的栅极长度。在该方法中，通过高介电常数材料和半导体材料彼此交替地外延生长，优选地以MBE形成量子阱。

8. 发明授权

US07521323B2 Method of fabricating a double gate field effect transistor device, and such a double gate field effect transistor device 有权
标题翻译：制造双栅场效应晶体管器件的方法，以及这种双栅场效应晶体管器件
公开(公告)号：US07521323B2
公开(公告)日：2009-04-21
申请号：US10570478
申请日：2004-08-12
申请人： Radu Catalin Surdeanu , Youri Ponomarev
发明人： Radu Catalin Surdeanu , Youri Ponomarev
IPC分类号： H01L21/336
CPC分类号： H01L29/66742 , H01L29/42384 , H01L29/4908 , H01L29/78621 , H01L29/78648
摘要： The present invention discloses a method of forming a double gate field effect transistor device, and such a device formed with the method. One starts with a semiconductor-on-insulator substrate, and forms a first gate, source, drain and extensions, and prepares the second gate. Then the substrate is bonded to a second carrier, exposing a second side of the semiconductor layer. Next, an annealing step is performed as a diffusionless annealing, which has the advantage that the semiconductor layer not only has a substantially even thickness, but also has a substantially flat surface. This ensures the best possible annealing action of said annealing step. Very sharp abruptness of the extensions is achieved, with very high activation of the dopants.
摘要翻译：本发明公开了一种形成双栅场效应晶体管器件的方法，以及用该方法形成的器件。一个从绝缘体上半导体衬底开始，并形成第一个栅极，源极，漏极和延伸部分，并准备第二个栅极。然后将衬底接合到第二载体，暴露半导体层的第二侧。接下来，进行退火步骤作为无扩散退火，其优点是半导体层不仅具有基本上均匀的厚度，而且具有基本平坦的表面。这确保了所述退火步骤的最佳退火作用。通过非常高的掺杂剂活化，实现了延伸部的非常尖锐的突然性。

9. 发明申请

US20070166922A1 Method of fabrication a double gate field effect transistor device and such a double gate field transistor device 有权
标题翻译：制造双栅场效应晶体管器件和这种双栅极场效应晶体管器件的方法
公开(公告)号：US20070166922A1
公开(公告)日：2007-07-19
申请号：US10570478
申请日：2004-08-12
申请人： Radu Surdeanu , Youri Ponomarev
发明人： Radu Surdeanu , Youri Ponomarev
IPC分类号： H01L21/336
CPC分类号： H01L29/66742 , H01L29/42384 , H01L29/4908 , H01L29/78621 , H01L29/78648
摘要： The present invention discloses a method of forming a double gate field effect transistor device, and such a device formed with the method. One starts with a semiconductor-on-insulator substrate, and forms a first gate, source, drain and extensions, and prepares the second gate. Then the substrate is bonded to a second carrier, exposing a second side of the semiconductor layer. Next, an annealing step is performed as a diffusionless annealing, which has the advantage that the semiconductor layer not only has a substantially even thickness, but also has a substantially flat surface. This ensures the best possible annealing action of said annealing step. Very sharp abruptness of the extensions is achieved, with very high activation of the dopants.
摘要翻译：本发明公开了一种形成双栅场效应晶体管器件的方法，以及用该方法形成的器件。一个从绝缘体上半导体衬底开始，并形成第一个栅极，源极，漏极和延伸部分，并准备第二个栅极。然后将衬底接合到第二载体，暴露半导体层的第二侧。接下来，进行退火步骤作为无扩散退火，其优点是半导体层不仅具有基本上均匀的厚度，而且具有基本平坦的表面。这确保了所述退火步骤的最佳退火作用。通过非常高的掺杂剂活化，实现了延伸部的非常尖锐的突然性。

10. 发明申请

US20060157685A1 Semiconductor device method of manfacturing a quantum well structure and a semiconductor device comprising such a quantum well structure 失效
标题翻译：制造量子阱结构的半导体器件方法和包括这种量子阱结构的半导体器件
公开(公告)号：US20060157685A1
公开(公告)日：2006-07-20
申请号：US10563483
申请日：2004-06-29
申请人： Youri Ponomarev
发明人： Youri Ponomarev
IPC分类号： H01L31/109
CPC分类号： H01L29/78696 , H01L29/1054 , H01L29/152 , H01L29/7782 , H01L29/7838 , H01L29/78687 , Y10S438/962
摘要： Consistent with example embodiments a semiconductor device and a method are disclosed for obtaining on a substrate a multilayer structure with a quantum well structure. The quantum well structure comprises a semiconductor layer sandwiched by insulating layers, wherein the material of the insulating layers has preferably a high dielectric constant. In a field effect transistor (FET) the quantum wells function as channels, allowing a higher drive current and a lower off current. Short channel effects are reduced. The multi-channel FET is suitable to operate even for sub-35 nm gate lengths. In the method the quantum wells are formed by epitaxial growth of the high dielectric constant material and the semiconductor material alternately on top of each other, preferably with molecular beam epitaxy (MBE).
摘要翻译：与示例性实施例一致，公开了用于在衬底上获得具有量子阱结构的多层结构的半导体器件和方法。量子阱结构包括被绝缘层夹在中间的半导体层，其中绝缘层的材料优选具有高介电常数。在场效应晶体管（FET）中，量子阱用作通道，允许更高的驱动电流和更低的截止电流。短信道效应降低。多通道FET适用于甚至对于35nm以下的栅极长度。在该方法中，量子阱通过高介电常数材料和半导体材料彼此交替地外延生长，优选地通过分子束外延（MBE）而形成。

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