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1. 发明授权

US07339843B2 Methods and circuits for programming addresses of failed memory cells in a memory device 失效
标题翻译：用于编程存储器件中的故障存储器单元的地址的方法和电路
公开(公告)号：US07339843B2
公开(公告)日：2008-03-04
申请号：US11229918
申请日：2005-09-19
申请人： Young-sun Min , Nam-jong Kim , Jong-hyun Choi
发明人： Young-sun Min , Nam-jong Kim , Jong-hyun Choi
IPC分类号： G11C29/00
CPC分类号： G11C29/82 , G11C17/18
摘要： A method of programming addresses of failed memory locations in a memory device can be provided by generating a plurality of fail address signals corresponding to a plurality of addresses of failed memory locations in the memory device and then programming the plurality of addresses of failed memory locations to programming cells for use by a redundant circuit during read or write operations to the plurality of addresses of failed memory locations.
摘要翻译：可以通过生成与存储器件中的故障存储器位置的多个地址相对应的多个故障地址信号，然后将失败存储器位置的多个地址编程到故障存储器位置的多个地址来对编程单元供读取或写入操作期间冗余电路用于故障存储单元的多个地址。

2. 发明申请

US20060062060A1 Methods and circuits for programming addresses of failed memory cells in a memory device 失效
标题翻译：用于编程存储器件中的故障存储器单元的地址的方法和电路
公开(公告)号：US20060062060A1
公开(公告)日：2006-03-23
申请号：US11229918
申请日：2005-09-19
申请人： Young-sun Min , Nam-jong Kim , Jong-hyun Choi
发明人： Young-sun Min , Nam-jong Kim , Jong-hyun Choi
IPC分类号： G11C29/00
CPC分类号： G11C29/82 , G11C17/18
摘要： A method of programming addresses of failed memory locations in a memory device can be provided by generating a plurality of fail address signals corresponding to a plurality of addresses of failed memory locations in the memory device and then programming the plurality of addresses of failed memory locations to programming cells for use by a redundant circuit during read or write operations to the plurality of addresses of failed memory locations.
摘要翻译：可以通过生成与存储器件中的故障存储器位置的多个地址相对应的多个故障地址信号，然后将失败存储器位置的多个地址编程到故障存储器位置的多个地址来对编程单元供读取或写入操作期间冗余电路用于故障存储单元的多个地址。

3. 发明授权

US07116591B2 Redundancy circuits and memory devices having a twist bitline scheme and methods of repairing defective cells in the same 失效
标题翻译：具有扭转位线方案的冗余电路和存储器件以及在其中修复缺陷单元的方法
公开(公告)号：US07116591B2
公开(公告)日：2006-10-03
申请号：US11089286
申请日：2005-03-24
申请人： Young-sun Min , Nam-jong Kim
发明人： Young-sun Min , Nam-jong Kim
IPC分类号： G11C29/18
CPC分类号： G11C7/18 , G11C11/401 , G11C11/4097 , G11C29/816
摘要： Redundancy circuits are provided for an integrated circuit memory device including a first memory cell block including a plurality of primary wordlines and a spare wordline, each associated with a plurality of memory cells; a second memory cell block including a plurality of primary wordlines and a spare wordline, each associated with a plurality of memory cells; and a plurality of bitlines extending across both the first and the second memory cell blocks the plurality of bitlines having a twisted bitline structure in which the bitlines are twisted between the first memory cell block and the second memory cell block and are not twisted within the respective memory cell blocks. The redundancy circuit is coupled to the primary and spare wordlines of both the first memory cell block and the second memory cell block. The redundancy circuit is also configured to select the spare wordline of the first memory cell block to replace one of the primary wordlines of the first memory cell block associated with a defective cell and to select the spare wordline of the second memory cell block to replace one of the primary wordlines of the second memory cell block associated with a defective cell so that data stored in spare cells connected to a selected spare wordline have a same data scramble as that of cells connected to the correspond.
摘要翻译：为集成电路存储器件提供冗余电路，该集成电路存储器件包括包括多个主字线和备用字线的第一存储器单元块，每个主字线与多个存储器单元相关联; 第二存储器单元块，其包括多个主字线和备用字线，每个与多个存储器单元相关联; 并且跨越第一和第二存储器单元延伸的多个位线阻止具有扭曲位线结构的多个位线，其中位线在第一存储器单元块和第二存储单元块之间被扭转，并且在相应的存储单元块。冗余电路耦合到第一存储器单元块和第二存储单元块的主字线和备用字线。冗余电路还被配置为选择第一存储器单元块的备用字线以替换与有缺陷单元相关联的第一存储器单元块的主字线之一，并选择第二存储单元块的备用字线以替换一个与有缺陷的单元相关联的第二存储单元块的主字线，使得存储在连接到所选备用字线的备用单元中的数据具有与连接到对应单元的数据相同的数据扰频。

4. 发明授权

US07317335B2 Level shifter with low leakage current 失效
标题翻译：电平移位器具有低漏电流
公开(公告)号：US07317335B2
公开(公告)日：2008-01-08
申请号：US11764241
申请日：2007-06-18
申请人： Young-sun Min , Nam-jong Kim
发明人： Young-sun Min , Nam-jong Kim
IPC分类号： H03K19/0175 , H03K19/094
CPC分类号： H03K3/356113
摘要： A voltage level shift circuit includes a first stage which receives an input signal having voltage levels Vcc and Vss, where Vcc>Vss, and which outputs complementary first and second intermediate signals, wherein the complementary first and second intermediate signals have voltage levels VIhigh and VIlow, where VIhigh>VIlow; and a second stage which receives the first and second intermediate signals, and which outputs complementary first and second output signals, wherein the complementary first and second output signals have voltage levels VOhigh and VOlow, where VOhigh>VOlow, wherein VIhigh>VOhigh or VIlow Vcc and VOlow
摘要翻译：电压电平移位电路包括第一级，其接收具有电压电平Vcc和Vss的输入信号，其中Vcc> Vss，并且其输出互补的第一和第二中间信号，其中互补的第一和第二中间信号具有电压电平VI _{高和VI _{低，其中VI高低> VI _{以及第二级，其接收所述第一和第二中间信号，并且输出互补的第一和第二输出信号，其中所述互补的第一和第二输出信号具有电压电平VO高电平和VO < / SUB>，其中VO VO _{低，其中VI高的低低，并且其中VO高/低Vcc和VO低Vss。}}}}

5. 发明申请

US20050276144A1 Temperature detector providing multiple detected temperature points using single branch and method of detecting shifted temperature 失效
标题翻译：温度检测器使用单个分支提供多个检测温度点和检测移位温度的方法
公开(公告)号：US20050276144A1
公开(公告)日：2005-12-15
申请号：US11151448
申请日：2005-06-14
申请人： Young-sun Min , Nam-jong Kim
发明人： Young-sun Min , Nam-jong Kim
IPC分类号： G11C7/00 , G11C7/04 , G11C11/406 , G11C29/02
CPC分类号： G11C29/028 , G11C7/04 , G11C11/401 , G11C11/406 , G11C11/40626 , G11C29/02 , G11C29/50016 , G11C2029/5002
摘要： A temperature detector and method of detecting a shifted temperature provides multiple detected temperature points using a single branch. The temperature detector generates multiple detected temperature points in response to temperature control signals sequentially generated in a single branch. Since a shifted temperature for the single branch is found and a trimming operation in response to the shifted temperature is carried out, the test time is reduced. Various refresh periods can be set in response to various trip point temperatures and thus power consumption of a DRAM can be decreased.
摘要翻译：温度检测器和检测转换温度的方法使用单个分支提供多个检测到的温度点。温度检测器响应于在单个分支中顺序产生的温度控制信号而产生多个检测到的温度点。由于发现单个分支的移位温度，并且执行响应于移位的温度的修整操作，所以测试时间减少。可以响应于各种跳变点温度来设置各种刷新周期，因此可以降低DRAM的功耗。

6. 发明申请

US20050276128A1 Redundancy circuits and memory devices having a twist bitline scheme and methods of repairing defective cells in the same 失效
标题翻译：具有扭转位线方案的冗余电路和存储器件以及在其中修复缺陷单元的方法
公开(公告)号：US20050276128A1
公开(公告)日：2005-12-15
申请号：US11089286
申请日：2005-03-24
申请人： Young-sun Min , Nam-jong Kim
发明人： Young-sun Min , Nam-jong Kim
IPC分类号： H01L21/8242 , G11C7/18 , G11C8/00 , G11C11/22 , G11C11/401 , G11C11/4063 , G11C11/4097 , G11C29/00 , G11C29/04 , H01L27/108
CPC分类号： G11C7/18 , G11C11/401 , G11C11/4097 , G11C29/816
摘要： Redundancy circuits are provided for an integrated circuit memory device including a first memory cell block including a plurality of primary wordlines and a spare wordline, each associated with a plurality of memory cells; a second memory cell block including a plurality of primary wordlines and a spare wordline, each associated with a plurality of memory cells; and a plurality of bitlines extending across both the first and the second memory cell blocks the plurality of bitlines having a twisted bitline structure in which the bitlines are twisted between the first memory cell block and the second memory cell block and are not twisted within the respective memory cell blocks. The redundancy circuit is coupled to the primary and spare wordlines of both the first memory cell block and the second memory cell block. The redundancy circuit is also configured to select the spare wordline of the first memory cell block to replace one of the primary wordlines of the first memory cell block associated with a defective cell and to select the spare wordline of the second memory cell block to replace one of the primary wordlines of the second memory cell block associated with a defective cell so that data stored in spare cells connected to a selected spare wordline have a same data scramble as that of cells connected to the correspond.
摘要翻译：为集成电路存储器件提供冗余电路，该集成电路存储器件包括包括多个主字线和备用字线的第一存储器单元块，每个主字线与多个存储器单元相关联; 第二存储器单元块，其包括多个主字线和备用字线，每个与多个存储器单元相关联; 并且跨越第一和第二存储器单元延伸的多个位线阻止具有扭曲位线结构的多个位线，其中位线在第一存储器单元块和第二存储单元块之间被扭转，并且在相应的存储单元块。冗余电路耦合到第一存储器单元块和第二存储单元块的主字线和备用字线。冗余电路还被配置为选择第一存储器单元块的备用字线以替换与有缺陷单元相关联的第一存储器单元块的主字线之一，并选择第二存储单元块的备用字线以替换一个与有缺陷的单元相关联的第二存储单元块的主字线，使得存储在连接到所选备用字线的备用单元中的数据具有与连接到对应单元的数据相同的数据扰频。

7. 发明授权

US07315792B2 Temperature detector providing multiple detected temperature points using single branch and method of detecting shifted temperature 失效
标题翻译：温度检测器使用单个分支提供多个检测温度点和检测移位温度的方法
公开(公告)号：US07315792B2
公开(公告)日：2008-01-01
申请号：US11151448
申请日：2005-06-14
申请人： Young-sun Min , Nam-jong Kim
发明人： Young-sun Min , Nam-jong Kim
IPC分类号： G01F15/00
CPC分类号： G11C29/028 , G11C7/04 , G11C11/401 , G11C11/406 , G11C11/40626 , G11C29/02 , G11C29/50016 , G11C2029/5002
摘要： A temperature detector and method of detecting a shifted temperature provides multiple detected temperature points using a single branch. The temperature detector generates multiple detected temperature points in response to temperature control signals sequentially generated in a single branch. Since a shifted temperature for the single branch is found and a trimming operation in response to the shifted temperature is carried out, the test time is reduced. Various refresh periods can be set in response to various trip point temperatures and thus power consumption of a DRAM can be decreased.
摘要翻译：温度检测器和检测转换温度的方法使用单个分支提供多个检测到的温度点。温度检测器响应于在单个分支中顺序产生的温度控制信号而产生多个检测到的温度点。由于发现单个分支的移位温度，并且执行响应于移位的温度的修整操作，所以测试时间减少。可以响应于各种跳变点温度来设置各种刷新周期，因此可以降低DRAM的功耗。

8. 发明申请

US20070236272A1 LEVEL SHIFTER WITH LOW LEAKAGE CURRENT 失效
标题翻译：低泄漏电流的液位变送器
公开(公告)号：US20070236272A1
公开(公告)日：2007-10-11
申请号：US11764241
申请日：2007-06-18
申请人： Young-sun Min , Nam-Jong Kim
发明人： Young-sun Min , Nam-Jong Kim
IPC分类号： H03L5/00
CPC分类号： H03K3/356113
摘要： A voltage level shift circuit includes a first stage which receives an input signal having voltage levels Vcc and Vss, where Vcc>Vss, and which outputs complementary first and second intermediate signals, wherein the complementary first and second intermediate signals have voltage levels VIhigh and VIlow, where VIhigh>VIlow; and a second stage which receives the first and second intermediate signals, and which outputs complementary first and second output signals, wherein the complementary first and second output signals have voltage levels VOhigh and VOlow, where VOhigh>VOlow, wherein VIhigh>VOhigh or VIlow Vcc and VOlow
摘要翻译：电压电平移位电路包括第一级，其接收具有电压电平Vcc和Vss的输入信号，其中Vcc> Vss，并且其输出互补的第一和第二中间信号，其中互补的第一和第二中间信号具有电压电平VI _{高和VI _{低，其中VI高低> VI _{以及第二级，其接收所述第一和第二中间信号，并且输出互补的第一和第二输出信号，其中所述互补的第一和第二输出信号具有电压电平VO高电平和VO < / SUB>，其中VO VO _{低，其中VI高的低 Vcc和VO低}}}}

9. 发明申请

US20070018710A1 Level shifter circuit of semiconductor memory device 审中-公开
标题翻译：半导体存储器件的电平移位电路
公开(公告)号：US20070018710A1
公开(公告)日：2007-01-25
申请号：US11416437
申请日：2006-05-02
申请人： Yun-jeong Choi , Young-sun Min , Young-min Jang
发明人： Yun-jeong Choi , Young-sun Min , Young-min Jang
IPC分类号： H03L5/00
CPC分类号： G11C5/14 , H03K3/012 , H03K3/356113
摘要： A level shifter circuit of a semiconductor memory device prevents a leakage current from being generated in a deep power down mode. The level shifter circuit comprises: a first NMOS transistor connected between a first node and a ground voltage terminal, wherein an input signal, which has a voltage level that is one of the ground voltage and a first power supply voltage, is input to a gate of the first NMOS transistor; a second NMOS transistor connected between a second node and the ground voltage terminal, wherein an inverted signal of the input signal is input to a gate of the second NMOS transistor; a first PMOS transistor which is connected between the first node and a second power supply voltage terminal and has a gate connected to the second node; a second PMOS transistor which is connected between the second node and the second power supply voltage terminal and has a gate connected to the first node; and a third NMOS transistor which has a drain connected to one of the first node and the second node and a gate connected to the other one of the first node and the second node and which maintains the first node and the second node each at one of two high and low logic levels when operating in a reduced power mode.
摘要翻译：半导体存储器件的电平移动器电路防止在深度掉电模式中产生漏电流。电平移位器电路包括：连接在第一节点和接地电压端子之间的第一NMOS晶体管，其中具有作为接地电压和第一电源电压之一的电压电平的输入信号被输入到门的第一NMOS晶体管; 连接在第二节点和接地电压端子之间的第二NMOS晶体管，其中输入信号的反相信号被输入到第二NMOS晶体管的栅极; 第一PMOS晶体管，其连接在第一节点和第二电源电压端子之间，并具有连接到第二节点的栅极; 第二PMOS晶体管，其连接在第二节点和第二电源电压端子之间，并具有连接到第一节点的栅极; 以及第三NMOS晶体管，其具有连接到所述第一节点和所述第二节点中的一个的漏极，以及连接到所述第一节点和所述第二节点中的另一节点的栅极，并且将所述第一节点和所述第二节点分别维持在在降低功耗模式下工作时的两个高低逻辑电平。

10. 发明授权

US07800972B2 Method of operating semiconductor memory device, semiconductor memory device and portable media system including the same 有权
标题翻译：操作半导体存储器件，半导体存储器件和包含该半导体存储器件的便携式介质系统的方法
公开(公告)号：US07800972B2
公开(公告)日：2010-09-21
申请号：US12003561
申请日：2007-12-28
申请人： Young-sun Min , Chang-ho Shin
发明人： Young-sun Min , Chang-ho Shin
IPC分类号： G11C7/00
CPC分类号： G11C5/14 , G11C5/148
摘要： A method of operating a semiconductor memory device may include initializing a first internal circuit in response to a first initialization signal based on an internal power voltage. The first initialization signal may be generated if the semiconductor memory device performs a power-up operation. The semiconductor memory device may enter a deep-power-down (DPD) mode without generating the first initialization signal. The first initialization signal may be generated if the semiconductor memory device exits the DPD mode.
摘要翻译：操作半导体存储器件的方法可以包括基于内部电源电压来响应于第一初始化信号初始化第一内部电路。如果半导体存储器件执行上电操作，则可以产生第一初始化信号。半导体存储器件可以进入深度掉电（DPD）模式而不产生第一初始化信号。如果半导体存储器件退出DPD模式，则可以产生第一初始化信号。

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