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1. 发明授权

US08254184B2 Semiconductor memory device having a latency controller 有权
标题翻译：具有等待时间控制器的半导体存储器件
公开(公告)号：US08254184B2
公开(公告)日：2012-08-28
申请号：US12820364
申请日：2010-06-22
申请人： Young-Soo Sohn , Jeong-Don Lim , Kwang-Il Park
发明人： Young-Soo Sohn , Jeong-Don Lim , Kwang-Il Park
IPC分类号： G11C7/00 , G11C5/14 , G11C8/00
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/109 , G11C7/222 , G11C2207/2272
摘要： A semiconductor memory device includes a latency controller which provides a power-saving effect. The latency controller includes a first-in first-out (FIFO) register. After a read command is applied, when a precharge command or power-down command is applied, the latency controller outputs a latency signal corresponding to the applied read command and blocks application of sampling and transmission clock signals to the FIFO register.
摘要翻译：半导体存储器件包括提供省电效果的等待时间控制器。等待时间控制器包括先进先出（FIFO）寄存器。在应用读命令之后，当应用预充电命令或掉电命令时，等待时间控制器输出与所应用的读命令对应的等待时间信号，并阻止采样和发送时钟信号的应用到FIFO寄存器。

2. 发明授权

US08189403B2 High speed linear differential amplifier 有权
标题翻译：高速线性差分放大器
公开(公告)号：US08189403B2
公开(公告)日：2012-05-29
申请号：US12817760
申请日：2010-06-17
申请人： Young-Soo Sohn , Jeong-Don Lim , Kwang-Il Park
发明人： Young-Soo Sohn , Jeong-Don Lim , Kwang-Il Park
IPC分类号： G11C7/00 , H03L7/00
CPC分类号： H03F3/45183 , H03F1/3211 , H03F3/45179 , H03F3/45654 , H03F2200/453 , H03F2200/78 , H03F2203/45382 , H03F2203/45384 , H03F2203/45454 , H03F2203/45466 , H03F2203/45702
摘要： A high speed linear differential amplifier (HSLDA) having automatic gain adjustment to maximize linearity regardless of manufacturing process, changes in temperature, or swing width change of the input signal. The HSLDA comprises a differential amplifier, and a control signal generator including a replica differential amplifier, a reference voltage generator, and a comparator. The comparator outputs a control signal that automatically adjusts the gain of the high speed linear differential amplifier and of the replica differential amplifier. The replica differential amplifier receives predetermined complementary voltages as input signals and outputs a replica output signal to the comparator. The reference voltage generator outputs a voltage to the comparator at which linearity of the output signal of the differential amplifier is maximized. The control signal equalizes the voltage level of the replica output signal and the reference voltage, and controls the gain of the differential amplifier.
摘要翻译：具有自动增益调整的高速线性差分放大器（HSLDA），以便与输入信号的制造过程，温度变化或摆幅宽度变化无关地最大化线性度。 HSLDA包括差分放大器和包括复制差分放大器，参考电压发生器和比较器的控制信号发生器。比较器输出一个自动调节高速线性差分放大器和复制差分放大器增益的控制信号。复制差分放大器接收预定的互补电压作为输入信号，并将复制输出信号输出到比较器。参考电压发生器向差分放大器的输出信号的线性度最大化的比较器输出电压。控制信号使复制输出信号的电压电平与参考电压相等，并控制差分放大器的增益。

3. 发明申请

US20110001562A1 HIGH SPEED LINEAR DIFFERENTIAL AMPLIFIER 有权
标题翻译：高速线性差分放大器
公开(公告)号：US20110001562A1
公开(公告)日：2011-01-06
申请号：US12817760
申请日：2010-06-17
申请人： Young-Soo Sohn , Jeong-Don Lim , Kwang-Il Park
发明人： Young-Soo Sohn , Jeong-Don Lim , Kwang-Il Park
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F1/3211 , H03F3/45179 , H03F3/45654 , H03F2200/453 , H03F2200/78 , H03F2203/45382 , H03F2203/45384 , H03F2203/45454 , H03F2203/45466 , H03F2203/45702
摘要： A high speed linear differential amplifier (HSLDA) having automatic gain adjustment to maximize linearity regardless of manufacturing process, changes in temperature, or swing width change of the input signal. The HSLDA comprises a differential amplifier, and a control signal generator including a replica differential amplifier, a reference voltage generator, and a comparator. The comparator outputs a control signal that automatically adjusts the gain of the high speed linear differential amplifier and of the replica differential amplifier. The replica differential amplifier receives predetermined complementary voltages as input signals and outputs a replica output signal to the comparator. The reference voltage generator outputs a voltage to the comparator at which linearity of the output signal of the differential amplifier is maximized. The control signal equalizes the voltage level of the replica output signal and the reference voltage, and controls the gain of the differential amplifier.
摘要翻译：具有自动增益调整的高速线性差分放大器（HSLDA），以便与输入信号的制造过程，温度变化或摆幅宽度变化无关地最大化线性度。 HSLDA包括差分放大器和包括复制差分放大器，参考电压发生器和比较器的控制信号发生器。比较器输出一个自动调节高速线性差分放大器和复制差分放大器增益的控制信号。复制差分放大器接收预定的互补电压作为输入信号，并将复制输出信号输出到比较器。参考电压发生器向差分放大器的输出信号的线性度最大化的比较器输出电压。控制信号使复制输出信号的电压电平与参考电压相等，并控制差分放大器的增益。

4. 发明申请

US20100329049A1 SEMICONDUCTOR MEMORY DEVICE HAVING A LATENCY CONTROLLER 有权
标题翻译：具有时间控制器的半导体存储器件
公开(公告)号：US20100329049A1
公开(公告)日：2010-12-30
申请号：US12820364
申请日：2010-06-22
申请人： YOUNG-SOO SOHN , Jeong-Don Lim , Kwang-Il Park
发明人： YOUNG-SOO SOHN , Jeong-Don Lim , Kwang-Il Park
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/109 , G11C7/222 , G11C2207/2272
摘要： A semiconductor memory device includes a latency controller which provides a power-saving effect. The latency controller includes a first-in first-out (FIFO) register. After a read command is applied, when a precharge command or power-down command is applied, the latency controller outputs a latency signal corresponding to the applied read command and blocks application of sampling and transmission clock signals to the FIFO register.
摘要翻译：半导体存储器件包括提供省电效果的等待时间控制器。等待时间控制器包括先进先出（FIFO）寄存器。在应用读命令之后，当应用预充电命令或掉电命令时，等待时间控制器输出与所应用的读命令对应的等待时间信号，并阻止采样和发送时钟信号的应用到FIFO寄存器。

5. 发明申请

US20100091600A1 CIRCUIT AND METHOD FOR SAMPLING VALID COMMAND USING EXTENDED VALID ADDRESS WINDOW IN DOUBLE PUMPED ADDRESS SCHEME MEMORY DEVICE 审中-公开
标题翻译：在双重抽取地址方案存储器件中使用扩展有效地址窗口采样有效命令的电路和方法
公开(公告)号：US20100091600A1
公开(公告)日：2010-04-15
申请号：US12635785
申请日：2009-12-11
申请人： Hyun-Jin Kim , Seong-Jin Jang , Jeong-Don Lim , Kwang-Il Park , Ho-Young Song , Woo-Jin Lee
发明人： Hyun-Jin Kim , Seong-Jin Jang , Jeong-Don Lim , Kwang-Il Park , Ho-Young Song , Woo-Jin Lee
IPC分类号： G11C8/00 , G11C8/18
CPC分类号： G06F12/02 , G11C7/1078 , G11C7/109
摘要： Provided are a circuit and method for sampling a valid command using a valid address window extended for a high-speed operation in a double pumped address scheme memory device. A method for extending the valid address window includes: inputting a valid command signal and a first address signal at the first cycle of a clock signal; inputting a second address signal at the second cycle of the clock signal; generating a decoded command signal and extended first and second internal address signals respectively in response to the command signal and the address signals; and latching and decoding the extended first and second internal address signals in response to the decoded command signal.
摘要翻译：提供了一种用于在双抽取地址方案存储器件中使用扩展用于高速操作的有效地址窗口来对有效命令进行采样的电路和方法。扩展有效地址窗口的方法包括：在时钟信号的第一周期输入有效的命令信号和第一地址信号; 在时钟信号的第二周期输入第二地址信号; 响应于命令信号和地址信号分别产生解码的命令信号和扩展的第一和第二内部地址信号; 以及响应于解码的命令信号来锁存和解码扩展的第一和第二内部地址信号。

6. 发明申请

US20080001626A1 Majority voter circuits and semiconductor devices including the same 有权
标题翻译：多数选民电路和半导体器件包括相同
公开(公告)号：US20080001626A1
公开(公告)日：2008-01-03
申请号：US11819600
申请日：2007-06-28
申请人： Seung-Jun Bae , Jeong-Don Lim , Gil-Shin Moon , Kwang-Il Park
发明人： Seung-Jun Bae , Jeong-Don Lim , Gil-Shin Moon , Kwang-Il Park
IPC分类号： H03K19/23
CPC分类号： H03K19/23
摘要： A majority voter circuit is configured to generate a selecting signal based on first input data and inverted first input data. The first input data and the inverted first input data each include an odd-number of bits, and the odd-number of bits include bits of a first type and bits of a second type. The generated selecting signal is indicative of which of the first type and the second type of bits in the first input data are in the majority.
摘要翻译：多数选民电路被配置为基于第一输入数据和反相的第一输入数据生成选择信号。第一输入数据和反相的第一输入数据都包括奇数位，奇数位包括第一类型的位和第二类型的位。所生成的选择信号表示第一输入数据中的第一类型和第二类型的比特大多数。

7. 发明授权

US07394720B2 Circuit and method for sampling valid command using extended valid address window in double pumped address scheme memory device 有权
标题翻译：在双泵浦地址方案存储器件中使用扩展有效地址窗口采样有效命令的电路和方法
公开(公告)号：US07394720B2
公开(公告)日：2008-07-01
申请号：US11560746
申请日：2006-11-16
申请人： Hyun-Jin Kim , Seong-Jin Jang , Jeong-Don Lim , Kwang-Il Park , Ho-Young Song , Woo-Jin Lee
发明人： Hyun-Jin Kim , Seong-Jin Jang , Jeong-Don Lim , Kwang-Il Park , Ho-Young Song , Woo-Jin Lee
IPC分类号： G11C8/00
CPC分类号： G06F12/02 , G11C7/1078 , G11C7/109
摘要： Provided are a circuit and method for sampling a valid command using a valid address window extended for a high-speed operation in a double pumped address scheme memory device. A method for extending the valid address window includes: inputting a valid command signal and a first address signal at the first cycle of a clock signal; inputting a second address signal at the second cycle of the clock signal; generating a decoded command signal and extended first and second internal address signals respectively in response to the command signal and the address signals; and latching and decoding the extended first and second internal address signals in response to the decoded command signal.
摘要翻译：提供了一种用于在双抽取地址方案存储器件中使用扩展用于高速操作的有效地址窗口来对有效命令进行采样的电路和方法。扩展有效地址窗口的方法包括：在时钟信号的第一周期输入有效的命令信号和第一地址信号; 在时钟信号的第二周期输入第二地址信号; 响应于命令信号和地址信号分别产生解码的命令信号和扩展的第一和第二内部地址信号; 以及响应于解码的命令信号来锁存和解码扩展的第一和第二内部地址信号。

8. 发明授权

US07688102B2 Majority voter circuits and semiconductor devices including the same 有权
标题翻译：多数选民电路和半导体器件包括相同
公开(公告)号：US07688102B2
公开(公告)日：2010-03-30
申请号：US11819600
申请日：2007-06-28
申请人： Seung-Jun Bae , Jeong-Don Lim , Gil-Shin Moon , Kwang-Il Park
发明人： Seung-Jun Bae , Jeong-Don Lim , Gil-Shin Moon , Kwang-Il Park
IPC分类号： H03K19/003
CPC分类号： H03K19/23
摘要： A majority voter circuit is configured to generate a selecting signal based on first input data and inverted first input data. The first input data and the inverted first input data each include an odd-number of bits, and the odd-number of bits include bits of a first type and bits of a second type. The generated selecting signal is indicative of which of the first type and the second type of bits in the first input data are in the majority.
摘要翻译：多数选民电路被配置为基于第一输入数据和反相的第一输入数据生成选择信号。第一输入数据和反相的第一输入数据都包括奇数位，奇数位包括第一类型的位和第二类型的位。所生成的选择信号表示第一输入数据中的第一类型和第二类型的比特大多数。

9. 发明授权

US08169268B2 Oscillation circuit and semiconductor device having the same 有权
标题翻译：振荡电路和具有相同的半导体器件
公开(公告)号：US08169268B2
公开(公告)日：2012-05-01
申请号：US12780985
申请日：2010-05-17
申请人： Ji-Hoon Lim , Jeong-Don Lim , Kwang-Il Park
发明人： Ji-Hoon Lim , Jeong-Don Lim , Kwang-Il Park
IPC分类号： H03K3/03 , G05F1/00 , H03B5/24
CPC分类号： H03K3/0315 , H03K3/017
摘要： An oscillation circuit, and a semiconductor device incorporating same, include: an oscillation unit with a plurality of inverters and configured to perform signal transmission between first and second nodes of the inverters such that each of the inverters performs an oscillation operation to generate clock signals having different phases when a control signal is activated, and latch a clock signal of the second node and cut off the signal transmission between the first and second nodes to stop the oscillation operations of the inverters when the control signal is deactivated; and a control unit to activate the control signal when an oscillation enable signal is activated, and deactivate the control signal using one of a clock signal output from an inverter connected to the second node and clock signals of which the phases lag that of a clock signal of the first node, when the oscillation enable signal is deactivated.
摘要翻译：振荡电路及其结合的半导体装置包括：具有多个反相器的振荡单元，其配置为在逆变器的第一和第二节点之间进行信号传输，使得每个反相器执行振荡操作以产生具有控制信号被激活时的不同相位，并且锁存第二节点的时钟信号并切断第一和第二节点之间的信号传输，以在控制信号被去激活时停止反相器的振荡操作; 以及控制单元，用于当振荡使能信号被激活时激活控制信号，并且使用从连接到第二节点的反相器输出的时钟信号中的一个和相位滞后于时钟信号的时钟信号来去激活控制信号当振荡使能信号被去激活时。

10. 发明授权

US07656742B2 Circuit and method for sampling valid command using extended valid address window in double pumped address scheme memory device 有权
标题翻译：在双泵浦地址方案存储器件中使用扩展有效地址窗口采样有效命令的电路和方法
公开(公告)号：US07656742B2
公开(公告)日：2010-02-02
申请号：US12128464
申请日：2008-05-28
申请人： Hyun-Jin Kim , Seong-Jin Jang , Jeong-Don Lim , Kwang-Il Park , Ho-Young Song , Woo-Jin Lee
发明人： Hyun-Jin Kim , Seong-Jin Jang , Jeong-Don Lim , Kwang-Il Park , Ho-Young Song , Woo-Jin Lee
IPC分类号： G11C8/00
CPC分类号： G06F12/02 , G11C7/1078 , G11C7/109
摘要： Provided are a circuit and method for sampling a valid command using a valid address window extended for a high-speed operation in a double pumped address scheme memory device. A method for extending the valid address window includes: inputting a valid command signal and a first address signal at the first cycle of a clock signal; inputting a second address signal at the second cycle of the clock signal; generating a decoded command signal and extended first and second internal address signals respectively in response to the command signal and the address signals; and latching and decoding the extended first and second internal address signals in response to the decoded command signal.
摘要翻译：提供了一种用于在双抽取地址方案存储器件中使用扩展用于高速操作的有效地址窗口来对有效命令进行采样的电路和方法。扩展有效地址窗口的方法包括：在时钟信号的第一周期输入有效的命令信号和第一地址信号; 在时钟信号的第二周期输入第二地址信号; 响应于命令信号和地址信号分别产生解码的命令信号和扩展的第一和第二内部地址信号; 以及响应于解码的命令信号来锁存和解码扩展的第一和第二内部地址信号。

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