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    • 5. 发明申请
    • PACKAGE MODULE OF BATTERY PROTECTION CIRCUIT
    • 电池保护电路封装模块
    • US20140347776A1
    • 2014-11-27
    • US14351321
    • 2012-08-20
    • Hyeok-Hwi NaYoung-Seok KimSang-Hoon AhnSung-Beum ParkSeung-Wook ParkHyun-Mok ChoSun-Bok ParkJae-Goo ParkHo-Suk Hwang
    • Hyeok-Hwi NaYoung-Seok KimSang-Hoon AhnSung-Beum ParkSeung-Wook ParkHyun-Mok ChoSun-Bok ParkJae-Goo ParkHo-Suk Hwang
    • H02J7/00H02H7/18H02H3/08H02H1/00
    • H02J7/0029H01L2224/48145H01L2224/49111H01L2924/19105H01M2/0217H01M2/0473H01M2/34H01M10/0525H01M10/4257H01M2010/4271H01M2200/00H01M2200/103H01M2200/106H02H1/0038H02H3/085H02H7/18Y02P70/54H01L2924/00012
    • The present invention pertains to a package module of a battery protection circuit, and the package module of the battery protection circuit according to the present invention comprises: a first internal connection terminal area and a second internal connection terminal area, which are respectively disposed at both edge parts thereof, and in which first and second internal connection terminals connected to a battery can provided with a bare cell are respectively disposed; an external connection terminal area, which is adjacent to the first internal connection terminal area, and in which a plurality of external connection terminals are disposed; and a protection circuit area comprising a device area in which a plurality of passive devices forming the battery protection circuit are disposed and a chip area, which is adjacent to the device area, and in which a protection IC and a dual FET chip forming the battery protection circuit are disposed, are disposed between the external connection terminal area and the second internal connection terminal area, and has a packaged structure to expose the plurality of external connection terminals on the upper surface thereof and expose the first internal connection terminal and the second internal connection terminal on the lower surface thereof. According to the present invention, a manufacturing process is minimized when compared with existing methods requiring a separate module manufacturing process, and a battery pack is easily formed and is able to be miniaturized and integrated.
    • 本发明涉及电池保护电路的封装模块,根据本发明的电池保护电路的封装模块包括:第一内部连接端子区域和第二内部连接端子区域,分别设置在两个 分别设置有与电池连接的第一和第二内部连接端子可以设置有裸电池的边缘部分, 外部连接端子区域,与第一内部连接端子区域相邻,并且其中设置有多个外部连接端子; 以及保护电路区域,包括其中设置有形成电池保护电路的多个无源器件的器件区域和与器件区域相邻的芯片区域,并且其中形成电池的保护IC和双FET芯片 保护电路设置在外部连接端子区域和第二内部连接端子区域之间,并且具有用于暴露其上表面上的多个外部连接端子的封装结构,并露出第一内部连接端子和第二内部连接端子 连接端子在其下表面。 根据本发明,与需要单独的模块制造工艺的现有方法相比,制造工艺最小化,并且电池组容易形成并且能够被小型化和集成。
    • 6. 发明授权
    • Apparatus and method for amplifying power in mobile terminal
    • 移动终端放大功率的装置和方法
    • US08565813B2
    • 2013-10-22
    • US13150523
    • 2011-06-01
    • Young-Seok Kim
    • Young-Seok Kim
    • H04W88/06
    • H03F3/24H03F1/56H03F3/189H03F2200/387
    • A transmission apparatus and a method thereof in a mobile terminal are provided. More particularly, an apparatus and a method for securing a space of a mobile terminal and reducing manufacturing costs by integrating power amplifying units into one module in the mobile terminal that supports a multi-mode are provided. The power amplifier of a mobile terminal includes a first amplifying unit and a second amplifying unit. The first amplifying unit defines a frequency of a GSM quad band as a low frequency band and a high frequency band, and then amplifies a signal of the low frequency band of the GSM quad band. The second amplifying unit amplifies a signal of the high frequency band of the GSM quad band and a signal of a TD-SCDMA band.
    • 提供了一种移动终端中的发送装置及其方法。 更具体地,提供了一种用于通过将功率放大单元集成到支持多模式的移动终端中的一个模块中来确保移动终端的空间并降低制造成本的装置和方法。 移动终端的功率放大器包括第一放大单元和第二放大单元。 第一放大单元将GSM四频带的频率定义为低频带和高频带,然后放大GSM四频带的低频带的信号。 第二放大单元放大GSM四频带的高频信号和TD-SCDMA频带的信号。
    • 8. 发明授权
    • Apparatus and method for measuring semiconductor device
    • 半导体器件测量装置及方法
    • US08324571B2
    • 2012-12-04
    • US12713261
    • 2010-02-26
    • Young-Seok KimJong-Sun PeakYoung-Nam KimHyung-Suk ChoSun-Jin KangBu-Dl Yoo
    • Young-Seok KimJong-Sun PeakYoung-Nam KimHyung-Suk ChoSun-Jin KangBu-Dl Yoo
    • G01N23/20
    • H01L22/20H01L22/12
    • An apparatus for measuring a semiconductor device is provided. The apparatus includes a beam emitter configured to irradiate an electron beam onto a sample having the entire region composed of a critical dimension (CD) region, which is formed by etching or development, and a normal region connected to the CD region, and an analyzer electrically connected to the beam emitter, and configured to select and set a wavelength range of a region in which a difference in reflectance between the CD region and the normal region occurs, after obtaining reflectance from the electron beam reflected by a surface of the sample according to the wavelength of the electron beam. A method of measuring a semiconductor device using the measuring apparatus is also provided. Therefore, it is possible to minimize a change in reflectance due to the thickness and properties of the semiconductor device, and set a wavelength range to monitor a specific wavelength, thereby accurately measuring and analyzing a CD value of a measurement part of the semiconductor device.
    • 提供了一种用于测量半导体器件的设备。 该装置包括:射束发射器,被配置为将电子束照射到具有由蚀刻或显影形成的临界尺寸(CD)区域和连接到CD区域的法线区域构成的整个区域的样品上;以及分析器 电连接到射束发射器,并且被配置为在从由样品表面反射的电子束获得反射率之后,选择和设置发生CD区域和法线区域之间的反射率差的区域的波长范围, 到电子束的波长。 还提供了使用测量装置测量半导体器件的方法。 因此,可以使半导体器件的厚度和特性的反射率变化最小化,并且设定波长范围来监视特定波长,从而精确地测量和分析半导体器件的测量部分的CD值。
    • 10. 发明申请
    • Method of Aligning a Substrate
    • 对准基板的方法
    • US20120008144A1
    • 2012-01-12
    • US13237509
    • 2011-09-20
    • Young-Seok KimJong-Sun Peak
    • Young-Seok KimJong-Sun Peak
    • G01B11/00
    • G03F9/7046H01L23/544H01L2223/5442H01L2223/54426H01L2223/54453H01L2924/0002H01L2924/00
    • In a method of aligning a substrate, a first alignment mark and a second alignment mark in a first shot region on the substrate may be sequentially identified. The substrate may be primarily aligned using identified any one of the first alignment mark and the second alignment mark. A used alignment mark and an unused alignment mark during the primary alignment process of the first alignment mark and the second alignment mark in a second shot region on the substrate may be sequentially identified. The substrate may be secondarily aligned using identified any one of the used alignment mark and the unused alignment mark during the primary alignment process. Thus, a time for identifying the alignment mark may be reduced.
    • 在对准衬底的方法中,可以顺序地识别衬底上的第一射出区域中的第一对准标记和第二对准标记。 可以使用所识别的第一对准标记和第二对准标记中的任一个来主要对准衬底。 可以顺序地识别在基板上的第二照射区域中的第一对准标记和第二对准标记的主对准处理期间使用的对准标记和未使用的对准标记。 可以在主对准过程期间使用所使用的对准标记和未使用的对准标记中的任何一个来二次对准衬底。 因此,可以减少用于识别对准标记的时间。