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1. 发明授权

US08076198B2 Method of fabricating nonvolatile memory device 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US08076198B2
公开(公告)日：2011-12-13
申请号：US12657092
申请日：2010-01-13
申请人： Hyosan Lee , Boun Yoon , Kuntack Lee , Donghyun Kim , Daehyuk Kang , Imsoo Park , Youngok Kim , Young-Hoo Kim , Sang Won Bae
发明人： Hyosan Lee , Boun Yoon , Kuntack Lee , Donghyun Kim , Daehyuk Kang , Imsoo Park , Youngok Kim , Young-Hoo Kim , Sang Won Bae
IPC分类号： H01L21/336 , H01L21/76 , H01L21/4763 , H01L21/461
CPC分类号： H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/66825 , H01L29/7881
摘要： A method of fabricating a nonvolatile memory device with a three-dimensional structure includes alternately stacking first and second material layers in two or more layers on a semiconductor substrate, forming trenches penetrating the stacked first and second material layers by performing a first etching process, and removing the second material layers exposed in the trenches by performing a second etching process. The first and second material layers are formed of materials that have the same main component but have different impurity contents, respectively.
摘要翻译：一种制造具有三维结构的非易失性存储器件的方法包括在半导体衬底上交替堆叠两层或多层第一和第二材料层，通过执行第一蚀刻工艺形成贯穿层叠的第一和第二材料层的沟槽，以及通过执行第二蚀刻工艺去除在沟槽中暴露的第二材料层。第一和第二材料层由具有相同主要成分但具有不同杂质含量的材料形成。

2. 发明授权

US09153597B2 Methods of manufacturing a three-dimensional semiconductor device 有权
标题翻译：制造三维半导体器件的方法
公开(公告)号：US09153597B2
公开(公告)日：2015-10-06
申请号：US13616254
申请日：2012-09-14
申请人： Young-Hoo Kim , Sang Won Bae , Kuntack Lee , Hyosan Lee
发明人： Young-Hoo Kim , Sang Won Bae , Kuntack Lee , Hyosan Lee
IPC分类号： H01L21/336 , H01L27/115 , H01L21/3105 , H01L21/311
CPC分类号： H01L27/11582 , H01L21/3105 , H01L21/31111 , H01L27/11556
摘要： The inventive concept provides methods of manufacturing three-dimensional semiconductor devices. In some embodiments, the methods include forming a stack structure including sacrificial layers and insulation layers, forming a trench penetrating the stack structure, forming a hydrophobic passivation element on the surfaces of the insulation layers that were exposed by the trench and selectively removing the sacrificial layers.
摘要翻译：本发明构思提供制造三维半导体器件的方法。在一些实施例中，所述方法包括形成包括牺牲层和绝缘层的堆叠结构，形成穿透堆叠结构的沟槽，在绝缘层的表面上形成疏水钝化元件，该绝缘层被沟槽暴露并选择性地去除牺牲层。

3. 发明申请

US20100178755A1 Method of fabricating nonvolatile memory device 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US20100178755A1
公开(公告)日：2010-07-15
申请号：US12657092
申请日：2010-01-13
申请人： Hyosan Lee , Boun Yoon , Kuntack Lee , Donghyun Kim , Daehyuk Kang , Imsoo Park , Youngok Kim , Young-Hoo Kim , Sang Won Bae
发明人： Hyosan Lee , Boun Yoon , Kuntack Lee , Donghyun Kim , Daehyuk Kang , Imsoo Park , Youngok Kim , Young-Hoo Kim , Sang Won Bae
IPC分类号： H01L21/20
CPC分类号： H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/66825 , H01L29/7881
摘要： A method of fabricating a nonvolatile memory device with a three-dimensional structure includes alternately stacking first and second material layers in two or more layers on a semiconductor substrate, forming trenches penetrating the stacked first and second material layers by performing a first etching process, and removing the second material layers exposed in the trenches by performing a second etching process. The first and second material layers are formed of materials that have the same main component but have different impurity contents, respectively.
摘要翻译：一种制造具有三维结构的非易失性存储器件的方法包括在半导体衬底上交替堆叠两层或多层第一和第二材料层，通过执行第一蚀刻工艺形成贯穿层叠的第一和第二材料层的沟槽，以及通过执行第二蚀刻工艺去除在沟槽中暴露的第二材料层。第一和第二材料层由具有相同主要成分但具有不同杂质含量的材料形成。

4. 发明申请

US20100181610A1 NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING NON-VOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器件的制造方法和非易失性存储器件的制造方法
公开(公告)号：US20100181610A1
公开(公告)日：2010-07-22
申请号：US12650076
申请日：2009-12-30
申请人： Young-Hoo Kim , Daehyuk Kang , Youngok Kim , Sang Won Bae , Boun Yoon , Kuntack Lee
发明人： Young-Hoo Kim , Daehyuk Kang , Youngok Kim , Sang Won Bae , Boun Yoon , Kuntack Lee
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L27/11582 , H01L29/7926
摘要： Provided are nonvolatile memory devices with a three-dimensional structure and methods of fabricating the same. The nonvolatile memory device includes conductive patterns three-dimensionally arranged on a semiconductor substrate, semiconductor patterns that extend from the semiconductor substrate and intersect one-side walls of the conductive patterns, charge storage layers interposed between the semiconductor patterns and one-side walls of the conductive patterns, and seed layer patterns interposed between the charge storage layers and one-side walls of the conductive patterns.
摘要翻译：提供具有三维结构的非易失性存储器件及其制造方法。非易失性存储器件包括三维地布置在半导体衬底上的导电图案，半导体图案从半导体衬底延伸并与导电图案的一侧壁相交，插入在半导体图案和半导体图案的一侧壁之间的电荷存储层导电图案和介于电荷存储层和导电图案的单侧壁之间的种子层图案。

5. 发明授权

US08120089B2 Non-volatile memory device and method for fabricating non-volatile memory device 有权
标题翻译：非易失性存储器件和用于制造非易失性存储器件的方法
公开(公告)号：US08120089B2
公开(公告)日：2012-02-21
申请号：US12650076
申请日：2009-12-30
申请人： Young-Hoo Kim , Daehyuk Kang , Youngok Kim , Sang Won Bae , Boun Yoon , Kuntack Lee
发明人： Young-Hoo Kim , Daehyuk Kang , Youngok Kim , Sang Won Bae , Boun Yoon , Kuntack Lee
IPC分类号： H01L29/76
CPC分类号： H01L29/792 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L27/11582 , H01L29/7926
摘要： Provided are nonvolatile memory devices with a three-dimensional structure and methods of fabricating the same. The nonvolatile memory device includes conductive patterns three-dimensionally arranged on a semiconductor substrate, semiconductor patterns that extend from the semiconductor substrate and intersect one-side walls of the conductive patterns, charge storage layers interposed between the semiconductor patterns and one-side walls of the conductive patterns, and seed layer patterns interposed between the charge storage layers and one-side walls of the conductive patterns.
摘要翻译：提供具有三维结构的非易失性存储器件及其制造方法。非易失性存储器件包括三维地布置在半导体衬底上的导电图案，半导体图案从半导体衬底延伸并与导电图案的一侧壁相交，插入在半导体图案和半导体图案的一侧壁之间的电荷存储层导电图案和介于电荷存储层和导电图案的单侧壁之间的种子层图案。

6. 发明申请

US20130078776A1 Methods of Manufacturing a Three-Dimensional Semiconductor Device 有权
标题翻译：制造三维半导体器件的方法
公开(公告)号：US20130078776A1
公开(公告)日：2013-03-28
申请号：US13616254
申请日：2012-09-14
申请人： Young-Hoo Kim , San Won Bae , Kuntack Lee , Hyosan Lee
发明人： Young-Hoo Kim , San Won Bae , Kuntack Lee , Hyosan Lee
IPC分类号： H01L21/336 , H01L21/30
CPC分类号： H01L27/11582 , H01L21/3105 , H01L21/31111 , H01L27/11556
摘要： The inventive concept provides methods of manufacturing three-dimensional semiconductor devices. In some embodiments, the methods include forming a stack structure including sacrificial layers and insulation layers, forming a trench penetrating the stack structure, forming a hydrophobic passivation element on the surfaces of the insulation layers that were exposed by the trench and selectively removing the sacrificial layers.
摘要翻译：本发明构思提供制造三维半导体器件的方法。在一些实施例中，所述方法包括形成包括牺牲层和绝缘层的堆叠结构，形成穿透堆叠结构的沟槽，在绝缘层的表面上形成疏水钝化元件，该绝缘层被沟槽暴露并选择性地去除牺牲层。

7. 发明申请

US20100200431A1 WAFER TEST METHOD AND WAFER TEST APPARATUS 失效
标题翻译： WAFER测试方法和WAFER测试设备
公开(公告)号：US20100200431A1
公开(公告)日：2010-08-12
申请号：US12704206
申请日：2010-02-11
申请人： Youngok Kim , Jeongnam Han , Changki Hong , Boun Yoon , Kuntack Lee , Young-Hoo Kim
发明人： Youngok Kim , Jeongnam Han , Changki Hong , Boun Yoon , Kuntack Lee , Young-Hoo Kim
IPC分类号： G01N27/26
CPC分类号： H01L22/14
摘要： The inventive concept provides a wafer test method and a wafer test apparatus. The wafer test method can recognize the amount of residuals generated in a sidewall of the metal-containing layer pattern and the extent of corrosion of a sidewall of the metal-containing layer pattern using the measured electric resistance by supplying an electrolyte so that the electrolyte is in contact with a portion of the metal-containing layer pattern in a predetermined chip region and measuring an electric resistance between a first electrode which is electrically in contact with the other portion of the metal-containing layer pattern and a second electrode which is in contact with the electrolyte in the predetermined region. Thus, a wafer test method and a wafer test apparatus can be embodied by an in-line method without dividing a wafer into each chip.
摘要翻译：本发明的概念提供了晶片测试方法和晶片测试装置。晶片测试方法可以通过提供电解质来确定含金属层图案的侧壁中产生的残留量以及含金属层图案的侧壁的腐蚀程度，使得电解质为与预定芯片区域中的含金属层图案的一部分接触，并且测量与含金属层图案的另一部分电接触的第一电极和接触的第二电极之间的电阻电解液在预定区域内。因此，可以通过在线方式来实现晶片测试方法和晶片测试装置，而不将晶片分成每个芯片。

8. 发明授权

US08228089B2 Wafer test method and wafer test apparatus 失效
标题翻译：晶圆试验方法和晶圆试验装置
公开(公告)号：US08228089B2
公开(公告)日：2012-07-24
申请号：US12704206
申请日：2010-02-11
申请人： Youngok Kim , Jeongnam Han , Changki Hong , Boun Yoon , Kuntack Lee , Young-Hoo Kim
发明人： Youngok Kim , Jeongnam Han , Changki Hong , Boun Yoon , Kuntack Lee , Young-Hoo Kim
IPC分类号： G01R31/26 , G01R31/08 , H01L21/66
CPC分类号： H01L22/14
摘要： The inventive concept provides a wafer test method and a wafer test apparatus. The wafer test method can recognize the amount of residuals generated in a sidewall of the metal-containing layer pattern and the extent of corrosion of a sidewall of the metal-containing layer pattern using the measured electric resistance by supplying an electrolyte so that the electrolyte is in contact with a portion of the metal-containing layer pattern in a predetermined chip region and measuring an electric resistance between a first electrode which is electrically in contact with the other portion of the metal-containing layer pattern and a second electrode which is in contact with the electrolyte in the predetermined region. Thus, a wafer test method and a wafer test apparatus can be embodied by an in-line method without dividing a wafer into each chip.
摘要翻译：本发明的概念提供了晶片测试方法和晶片测试装置。晶片测试方法可以通过提供电解质来确定含金属层图案的侧壁中产生的残留量以及含金属层图案的侧壁的腐蚀程度，使得电解质为与预定芯片区域中的含金属层图案的一部分接触，并且测量与含金属层图案的另一部分电接触的第一电极和接触的第二电极之间的电阻电解液在预定区域内。因此，可以通过在线方式来实现晶片测试方法和晶片测试装置，而不将晶片分成每个芯片。

9. 发明申请

US20150368557A1 METAL ETCHANT COMPOSITIONS AND METHODS OF FABRICATING A SEMICONDUCTOR DEVICE USING THE SAME 审中-公开
标题翻译：金属蚀刻剂组合物和使用其制造半导体器件的方法
公开(公告)号：US20150368557A1
公开(公告)日：2015-12-24
申请号：US14312043
申请日：2014-06-23
申请人： Hyosan Lee , Yongsun Ko , Kyoungseob Kim , Kuntack Lee , Jihoon Jeong , Chen Lin , Christopher K. Ober
发明人： Hyosan Lee , Yongsun Ko , Kyoungseob Kim , Kuntack Lee , Jihoon Jeong , Chen Lin , Christopher K. Ober
IPC分类号： C09K13/00
CPC分类号： C09K13/08 , C23F1/18 , C23F1/20 , C23F1/26 , H01L21/02063 , H01L21/0273 , H01L21/31111 , H01L21/32134 , H01L21/67017 , H01L21/6708 , H01L21/76802 , H01L24/03 , H01L24/11 , H01L2224/03614 , H01L2224/0401 , H01L2224/05571 , H01L2224/05624 , H01L2224/05647 , H01L2224/05666 , H01L2224/05681 , H01L2224/05684 , H01L2924/04941 , H01L2924/04953 , H01L2924/20102 , H01L2924/20103 , H01L2924/20104
摘要： The present inventive concepts provide metal etchant compositions and methods of fabricating a semiconductor device using the same. The metal etchant composition includes an organic peroxide in a range of about 0.1 wt % to about 20 wt %, an organic acid in a range of about 0.1 wt % to about 70 wt %, and an alcohol-based solvent in a range of about 10 wt % to about 99.8 wt %. The metal etchant composition may be used in an anhydrous system.
摘要翻译：本发明构思提供金属蚀刻剂组合物和使用其制造半导体器件的方法。金属蚀刻剂组合物包括约0.1重量％至约20重量％范围内的有机过氧化物，约0.1重量％至约70重量％范围内的有机酸和约0.001重量％至约70重量％范围内的醇系溶剂 10重量％至约99.8重量％。金属蚀刻剂组合物可用于无水体系中。

10. 发明授权

US10155903B2 Metal etchant compositions and methods of fabricating a semiconductor device using the same 有权
公开(公告)号：US10155903B2
公开(公告)日：2018-12-18
申请号：US15075709
申请日：2016-03-21
申请人： Hyosan Lee , Yongsun Ko , Kyoungseob Kim , Kuntack Lee , Jihoon Jeong , Chen Lin , Christopher K. Ober
发明人： Hyosan Lee , Yongsun Ko , Kyoungseob Kim , Kuntack Lee , Jihoon Jeong , Chen Lin , Christopher K. Ober
IPC分类号： B44C1/22 , C23F1/00 , C03C15/00 , C03C25/68 , C25F3/00 , C09K13/08 , H01L21/027 , H01L21/311 , H01L21/768 , H01L23/00 , C23F1/26 , H01L21/02 , H01L21/3213 , H01L21/67 , C23F1/18 , C23F1/20
摘要： The present inventive concepts provide metal etchant compositions and methods of fabricating a semiconductor device using the same. The metal etchant composition includes an organic peroxide in a range of about 0.1 wt % to about 20 wt %, an organic acid in a range of about 0.1 wt % to about 70 wt %, and an alcohol-based solvent in a range of about 10 wt % to about 99.8 wt %. The metal etchant composition may be used in an anhydrous system.

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