专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08058863B2 Band-gap reference voltage generator 有权
标题翻译：带隙基准电压发生器
公开(公告)号：US08058863B2
公开(公告)日：2011-11-15
申请号：US12428425
申请日：2009-04-22
申请人： Young Kyun Cho , Young Deuk Jeon , Jae Won Nam , JongKee Kwon
发明人： Young Kyun Cho , Young Deuk Jeon , Jae Won Nam , JongKee Kwon
IPC分类号： G05F3/16
CPC分类号： G05F3/30
摘要： A band-gap reference voltage generator is provided. N-channel metal oxide semiconductor (NMOS) transistors are respectively connected to bipolar transistors in parallel. A Complementary To Absolute Temperature (CTAT) voltage that is inversely proportional to absolute temperature is reduced by a threshold voltage of the NMOS transistor. A weight for a temperature coefficient of a Proportional To Absolute Temperature (PTAT) voltage that is directly proportional to absolute temperature is reduced and a resistance ratio for a temperature coefficient of 0 is reduced by about ½, thereby miniaturizing the band-gap reference voltage generator. A reference voltage lower than or equal to 1 V can be provided by resistors respectively connected to the bipolar transistors in parallel.
摘要翻译：提供带隙参考电压发生器。 N沟道金属氧化物半导体（NMOS）晶体管分别并联连接到双极晶体管。与绝对温度成反比的绝对温度互补（CTAT）电压降低了NMOS晶体管的阈值电压。与绝对温度成正比的比例绝对温度（PTAT）电压的温度系数的重量减小，温度系数为0的电阻比减小约1/2，从而使带隙基准电压发生器。可以通过并联连接到双极晶体管的电阻器提供低于或等于1V的参考电压。

2. 发明授权

US08164497B2 Pipeline analog-to-digital converter 有权
标题翻译：管道模数转换器
公开(公告)号：US08164497B2
公开(公告)日：2012-04-24
申请号：US12777910
申请日：2010-05-11
申请人： Jae Won Nam , Young Deuk Jeon , Young Kyun Cho , Jong Kee Kwon
发明人： Jae Won Nam , Young Deuk Jeon , Young Kyun Cho , Jong Kee Kwon
IPC分类号： H03M1/00
CPC分类号： H03M1/0836 , H03M1/168
摘要： Provided is a pipeline analog-to-digital converter (ADC) without a front-end sample-and-hold amplifier (SHA). To minimize a sampling error occurring between a flash ADC and a multiplying digital-to-analog converter (MDAC) of a first sub-ranging ADC due to removal of a front-end SHA, a delay time of a preamplifier included in the flash ADC is calculated, and the flash ADC samples an analog input signal later by the delay time than the MDAC. Accordingly, the pipeline ADC can minimize a sampling error without using a front-end SHA, and its chip area and power consumption can be reduced.
摘要翻译：提供了一种没有前端采样和保持放大器（SHA）的流水线模数转换器（ADC）。为了最小化由于去除前端SHA而导致的闪存ADC和第一子范围ADC的乘法数模转换器（MDAC）之间的采样误差，包括在闪存ADC中的前置放大器的延迟时间并且闪速ADC比模拟输入信号稍后采样延迟时间比MDAC。因此，流水线ADC可以在不使用前端SHA的情况下最小化采样误差，并且可以减少其芯片面积和功耗。

3. 发明授权

US07999719B2 Multi-stage successive approximation register analog-to-digital converter and analog-to-digital converting method using the same 有权
标题翻译：多级逐次逼近寄存器模数转换器和使用其的模数转换方法
公开(公告)号：US07999719B2
公开(公告)日：2011-08-16
申请号：US12433764
申请日：2009-04-30
申请人： Young Deuk Jeon , Young Kyun Cho , Jae Won Nam , Jong Kee Kwon
发明人： Young Deuk Jeon , Young Kyun Cho , Jae Won Nam , Jong Kee Kwon
IPC分类号： H03M1/38
CPC分类号： H03M1/164 , H03M1/468
摘要： A multi-stage Successive Approximation Register Analog-to-Digital Converter (SAR ADC) and an analog-to-digital converting method using the same are provided. The multi-stage SAR ADC connects small-size and low-power SAR ADCs in multiple stages, thereby reducing a whole chip size and power consumption. The analog-to-digital converting method simultaneously performs analog-to-digital conversions in the SAR ADCs connected in the multiple stages, thereby reducing an analog-to-digital conversion time and maintaining an operating rate of several tens of MHz to several hundreds of MHz similar to that of a pipeline ADC.
摘要翻译：提供了多级连续近似寄存器模数转换器（SAR ADC）和使用其的模数转换方法。多级SAR ADC多级连接小尺寸和低功耗SAR ADC，从而降低整个芯片尺寸和功耗。模数转换方法同时在多级连接的SAR ADC中执行模数转换，从而减少模数转换时间，并将几十MHz至几百 MHz与流水线ADC类似。

4. 发明申请

US20100156469A1 HIGH-SPEED MULTI-STAGE VOLTAGE COMPARATOR 失效
标题翻译：高速多级电压比较器
公开(公告)号：US20100156469A1
公开(公告)日：2010-06-24
申请号：US12507357
申请日：2009-07-22
申请人： Young Kyun Cho , Young Deuk Jeon , Jae Won Nam , Jong Kee Kwon
发明人： Young Kyun Cho , Young Deuk Jeon , Jae Won Nam , Jong Kee Kwon
IPC分类号： H03F3/45
CPC分类号： H03F3/45475 , H03F3/45968 , H03F2203/45212
摘要： A high-speed multi-stage voltage comparator is provided. The multi-stage voltage comparator is configured to eliminate offset from outputs of preamplifiers through respective offset-cancellation switches, and to reset the outputs of the preamplifiers through respective reset switches to reduce an output recovery time. Thus, the multi-stage voltage comparator operates with high accuracy and at a high speed, so that it can be usefully applied to an analog-to-digital converter (ADC), and particularly, a high-speed successive approximation register ADC (SAR ADC).
摘要翻译：提供了一个高速多级电压比较器。多级电压比较器被配置为消除通过相应的偏移消除开关的前置放大器的输出的偏移，并且通过相应的复位开关复位前置放大器的输出以减少输出恢复时间。因此，多级电压比较器以高精度和高速运行，从而可以有效地应用于模数转换器（ADC），特别是高速逐次逼近寄存器ADC（SAR） ADC）。

5. 发明申请

US20100052643A1 BAND-GAP REFERENCE VOLTAGE GENERATOR 有权
标题翻译：带隙参考电压发生器
公开(公告)号：US20100052643A1
公开(公告)日：2010-03-04
申请号：US12428425
申请日：2009-04-22
申请人： Young Kyun Cho , Young Deuk Jeon , Jae Won Nam , Jong Kee Kwon
发明人： Young Kyun Cho , Young Deuk Jeon , Jae Won Nam , Jong Kee Kwon
IPC分类号： G05F3/16
CPC分类号： G05F3/30
摘要： A band-gap reference voltage generator is provided. N-channel metal oxide semiconductor (NMOS) transistors are respectively connected to bipolar transistors in parallel. A Complementary To Absolute Temperature (CTAT) voltage that is inversely proportional to absolute temperature is reduced by a threshold voltage of the NMOS transistor. A weight for a temperature coefficient of a Proportional To Absolute Temperature (PTAT) voltage that is directly proportional to absolute temperature is reduced and a resistance ratio for a temperature coefficient of 0 is reduced by about ½, thereby miniaturizing the band-gap reference voltage generator. A reference voltage lower than or equal to 1 V can be provided by resistors respectively connected to the bipolar transistors in parallel.
摘要翻译：提供带隙参考电压发生器。 N沟道金属氧化物半导体（NMOS）晶体管分别并联连接到双极晶体管。与绝对温度成反比的绝对温度互补（CTAT）电压降低了NMOS晶体管的阈值电压。与绝对温度成正比的比例绝对温度（PTAT）电压的温度系数的重量减小，温度系数为0的电阻比减小约1/2，从而使带隙基准电压发生器。可以通过并联连接到双极晶体管的电阻器提供低于或等于1V的参考电压。

6. 发明授权

US08164504B2 Successive approximation register analog-digital converter and method for operating the same 有权
标题翻译：逐次逼近寄存器模数转换器及其操作方法
公开(公告)号：US08164504B2
公开(公告)日：2012-04-24
申请号：US12882421
申请日：2010-09-15
申请人： Young Kyun Cho , Young Deuk Jeon , Jae Won Nam , Jong Kee Kwon
发明人： Young Kyun Cho , Young Deuk Jeon , Jae Won Nam , Jong Kee Kwon
IPC分类号： H03M1/12
CPC分类号： H03M1/0678 , H03M1/0682 , H03M1/468
摘要： A successive approximation resistor analog digital converter (SAR ADC) includes a first conversion unit including a correction capacitor array and a bit capacitor array 2V-1 less than the number of a bit, a second conversion unit configured to differentially operate with the first conversion unit, a comparator configured to output a voltage of a high level or a low level of each capacitor according to output voltages of the first and second conversion units, a successive approximation register (SAR) logic unit configured to receive an output voltage of the comparator to convert the received output voltage into a digital signal, and a correction logic unit configured to receive the digital signal converted by the SAR logic unit and to correct a digital signal of the bit capacitor array using a correction digital signal of the correction capacitor array of the received digital signal.
摘要翻译：逐次逼近电阻模拟数字转换器（SAR ADC）包括第一转换单元，其包括校正电容器阵列和小于位数的位电容器阵列2V-1，第二转换单元，被配置为与第一转换单元差分地操作，比较器，被配置为根据第一和第二转换单元的输出电压输出每个电容器的高电平或低电平的电压;逐次逼近寄存器（SAR）逻辑单元，被配置为将比较器的输出电压接收到将接收到的输出电压转换成数字信号，以及校正逻辑单元，被配置为接收由SAR逻辑单元转换的数字信号，并且使用校正电容器阵列的校正数字信号来校正位电容器阵列的数字信号接收数字信号。

7. 发明申请

US20110227774A1 SUCCESSIVE APPROXIMATION REGISTER ANALOG-DIGITAL CONVERTER AND METHOD FOR OPERATING THE SAME 有权
标题翻译：连续逼近寄存器模拟数字转换器及其操作方法
公开(公告)号：US20110227774A1
公开(公告)日：2011-09-22
申请号：US12882421
申请日：2010-09-15
申请人： Young Kyun Cho , Young Deuk Jeon , Jae Won Nam , Jong Kee Kwon
发明人： Young Kyun Cho , Young Deuk Jeon , Jae Won Nam , Jong Kee Kwon
IPC分类号： H03M1/12
CPC分类号： H03M1/0678 , H03M1/0682 , H03M1/468
摘要： A successive approximation resistor analog digital converter (SAR ADC) includes a first conversion unit including a correction capacitor array and a bit capacitor array 2ν-1 less than the number of a bit, a second conversion unit configured to differentially operate with the first conversion unit, a comparator configured to output a voltage of a high level or a low level of each capacitor according to output voltages of the first and second conversion units, a successive approximation register (SAR) logic unit configured to receive an output voltage of the comparator to convert the received output voltage into a digital signal, and a correction logic unit configured to receive the digital signal converted by the SAR logic unit and to correct a digital signal of the bit capacitor array using a correction digital signal of the correction capacitor array of the received digital signal.
摘要翻译：逐次逼近电阻模拟数字转换器（SAR ADC）包括第一转换单元，其包括校正电容器阵列和小于位数的位电容器阵列2＆ngr; -1，第二转换单元，被配置为与第一转换差分地操作单元，比较器，被配置为根据第一和第二转换单元的输出电压输出每个电容器的高电平或低电平的电压;逐次逼近寄存器（SAR）逻辑单元，被配置为接收比较器的输出电压将所接收的输出电压转换为数字信号，以及校正逻辑单元，被配置为接收由SAR逻辑单元转换的数字信号，并使用校正电容阵列的校正数字信号校正位电容阵列的数字信号接收数字信号。

8. 发明授权

US07978117B2 Multi-stage dual successive approximation register analog-to-digital convertor and method of performing analog-to-digital conversion using the same 有权
标题翻译：多级双逐次逼近寄存器模数转换器和使用其进行模数转换的方法
公开(公告)号：US07978117B2
公开(公告)日：2011-07-12
申请号：US12539406
申请日：2009-08-11
申请人： Young Deuk Jeon , Young Kyun Cho , Jae Won Nam , Jong Kee Kwon
发明人： Young Deuk Jeon , Young Kyun Cho , Jae Won Nam , Jong Kee Kwon
IPC分类号： H03M1/34
CPC分类号： H03M1/164 , H03M1/1215 , H03M1/468 , H03M1/804
摘要： A multi-stage dual successive approximation register analog-to-digital converter (SAR ADC) and a method of performing analog-to-digital conversion using the same are provided. The multi-stage dual SAR ADC includes: a plurality of SAR ADC stages for converting an analog input voltage into a predetermined bit digital signal, each SAR ADC stage being serially connected to one another and including two SAR ADCs; and at least one residue amplifier respectively connected between every two successive SAR ADC stages, amplifying residue voltage output from a previous SAR ADC stage to output the amplified residue voltage to a next SAR ADC stage. The two SAR ADCs of the previous SAR ADC stage share the residue amplifier.
摘要翻译：提供了多级双逐次逼近寄存器模数转换器（SAR ADC）和使用其进行模数转换的方法。多级双SAR ADC包括：多个SAR ADC级，用于将模拟输入电压转换为预定位数字信号，每个SAR ADC级串联连接并包括两个SAR ADC; 和分别连接在每两个连续的SAR ADC级之间的至少一个残余放大器，放大从先前的SAR ADC级输出的剩余电压，以将放大的残余电压输出到下一个SAR ADC级。前一个SAR ADC级的两个SAR ADC共享残留放大器。

9. 发明授权

US07893860B2 Successive approximation register analog-digital converter and method of driving the same 有权
标题翻译：逐次逼近寄存器模数转换器及其驱动方法
公开(公告)号：US07893860B2
公开(公告)日：2011-02-22
申请号：US12472375
申请日：2009-05-27
申请人： Young Kyun Cho , Young Deuk Jeon , Jae Won Nam , Jong Kee Kwon
发明人： Young Kyun Cho , Young Deuk Jeon , Jae Won Nam , Jong Kee Kwon
IPC分类号： H03M1/38
CPC分类号： H03M1/069 , H03M1/0607 , H03M1/468 , H03M1/804
摘要： A successive approximation register (SAR) analog-digital converter (ADC) and a method of driving the same are provided. The SAR ADC includes a first converting unit including a bit capacitor array corresponding to the number of bits and a correction capacitor array, a comparator outputting a high or low voltage corresponding to each capacitor according to an output voltage of the converting unit, and a correction unit correcting the output of the bit capacitor according to the output of the correction capacitor array among the high or low output of the comparator. Therefore, two bits having the same capacitance as a least significant bit (LSB) enable a digital output error to be corrected, so that a spurious free dynamic range (SFDR) of the signal converter is increased, and a signal to noise and distortion ratio (SNDR) of an output signal is improved.
摘要翻译：提供逐次逼近寄存器（SAR）模数转换器（ADC）及其驱动方法。 SAR ADC包括：第一转换单元，包括与位数相对应的位电容阵列和校正电容器阵列;比较器，根据转换单元的输出电压输出对应于每个电容器的高电压或低电压;以及校正单元根据比较器的高或低输出中的校正电容器阵列的输出校正位电容器的输出。因此，具有与最低有效位（LSB）相同的电容的两个位使得能够校正数字输出误差，使得信号转换器的无杂散动态范围（SFDR）增加，并且信噪比和失真比（SNDR）的输出信号得到改善。

10. 发明申请

US20110032134A1 DIGITAL-TO-ANALOG CONVERTER 有权
标题翻译：数字到模拟转换器
公开(公告)号：US20110032134A1
公开(公告)日：2011-02-10
申请号：US12773768
申请日：2010-05-04
申请人： Young Kyun Cho , Young Deuk Jeon , Jae Won Nam , Jong Kee Kwon
发明人： Young Kyun Cho , Young Deuk Jeon , Jae Won Nam , Jong Kee Kwon
IPC分类号： H03M1/66
CPC分类号： H03M1/0682 , H03M1/468 , H03M1/68 , H03M1/682 , H03M1/804 , H03M1/806
摘要： A digital-to-analog converter (DAC) is provided. The DAC includes a positive converter, a negative converter, and a comparator for receiving outputs of the positive converter and the negative converter, comparing the outputs with a reference voltage, and generating an output voltage. Each of the positive converter and the negative converter includes an upper-bit converter including a plurality of bit capacitors corresponding to respective upper bits, a lower-bit converter including a plurality of bit capacitors corresponding to respective lower bits, and a coupling capacitor for connecting the upper-bit converter with the lower-bit converter in series. Each of the positive converter and the negative converter receives a bias voltage to have a uniform offset when converting the respective bits. Accordingly, it is possible to obtain a high resolution using a small area. Also, the number of capacitors can be reduced, and the capacitance of a unit capacitor can be maximized. Consequently, it is possible to minimize heat noise and device mismatching.
摘要翻译：提供了数模转换器（DAC）。 DAC包括正转换器，负转换器和用于接收正转换器和负转换器的输出的比较器，将输出与参考电压进行比较，并产生输出电压。正转换器和负转换器中的每个包括具有对应于各高位的多个位电容器的高位转换器，包括对应于各低位的多个位电容器的低位转换器和用于连接的耦合电容器低位转换器与低位转换器串联。正转换器和负转换器中的每一个在转换各个位时接收偏置电压以具有均匀的偏移。因此，可以使用小面积获得高分辨率。此外，可以减少电容器的数量，并且可以使单位电容器的电容最大化。因此，可以最小化热噪声和器件不匹配。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式