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1. 发明申请

US20120207266A1 SHIFT REGISTER CIRCUIT 审中-公开
标题翻译：移位寄存器电路
公开(公告)号：US20120207266A1
公开(公告)日：2012-08-16
申请号：US13455808
申请日：2012-04-25
申请人： Youichi TOBITA , Isao Nojiri , Seiichiro Mori , Takashi Miyayama
发明人： Youichi TOBITA , Isao Nojiri , Seiichiro Mori , Takashi Miyayama
IPC分类号： G11C19/00
CPC分类号： G11C19/28 , G09G3/3266 , G09G3/3677 , G09G2300/0408 , G09G2310/0286 , G09G2320/0233 , G11C19/184
摘要： A shift register circuit comprises a first transistor connected between a clock terminal and an output terminal, a second transistor for charging a control electrode of the first transistor in response to activation of an output signal of the preceding stage, a third transistor for discharging the control electrode of the first transistor, an inverter using a control electrode of the third transistor as an output end, and a fourth transistor which discharges an input end of the inverter at power-off and is turned off after power-on. A fifth transistor which is a load element of the inverter charges the control electrode of the third transistor at power-on. It is thereby possible to initialize the respective levels of the nodes without any external initialization signal and prevent a decrease in the level change rate of the output signal in the shift register circuit.
摘要翻译：移位寄存器电路包括连接在时钟端子和输出端子之间的第一晶体管，用于响应于前一级的输出信号的激活而对第一晶体管的控制电极进行充电的第二晶体管，用于对控制器进行放电的第三晶体管第一晶体管的电极，使用第三晶体管的控制电极作为输出端的反相器，以及在断电时对逆变器的输入端进行放电并在通电之后被截止的第四晶体管。作为逆变器的负载元件的第五晶体管在通电时对第三晶体管的控制电极进行充电。从而可以初始化节点的各个级别而没有任何外部初始化信号，并且防止移位寄存器电路中的输出信号的电平变化率的降低。

2. 发明授权

US08194817B2 Shift register circuit 有权
标题翻译：移位寄存器电路
公开(公告)号：US08194817B2
公开(公告)日：2012-06-05
申请号：US12951705
申请日：2010-11-22
申请人： Youichi Tobita , Isao Nojiri , Seiichiro Mori , Takashi Miyayama
发明人： Youichi Tobita , Isao Nojiri , Seiichiro Mori , Takashi Miyayama
IPC分类号： G11C19/00
CPC分类号： G11C19/28 , G09G3/3266 , G09G3/3677 , G09G2300/0408 , G09G2310/0286 , G09G2320/0233 , G11C19/184
摘要： A shift register circuit comprises a first transistor connected between a clock terminal and an output terminal, a second transistor for charging a control electrode of the first transistor in response to activation of an output signal of the preceding stage, a third transistor for discharging the control electrode of the first transistor, an inverter using a control electrode of the third transistor as an output end, and a fourth transistor which discharges an input end of the inverter at power-off and is turned off after power-on. A fifth transistor which is a load element of the inverter charges the control electrode of the third transistor at power-on. It is thereby possible to initialize the respective levels of the nodes without any external initialization signal and prevent a decrease in the level change rate of the output signal in the shift register circuit.
摘要翻译：移位寄存器电路包括连接在时钟端子和输出端子之间的第一晶体管，用于响应于前一级的输出信号的激活而对第一晶体管的控制电极进行充电的第二晶体管，用于对控制器进行放电的第三晶体管第一晶体管的电极，使用第三晶体管的控制电极作为输出端的反相器，以及在断电时对逆变器的输入端进行放电并在通电之后被截止的第四晶体管。作为逆变器的负载元件的第五晶体管在通电时对第三晶体管的控制电极进行充电。从而可以初始化节点的各个级别而没有任何外部初始化信号，并且防止移位寄存器电路中的输出信号的电平变化率的降低。

3. 发明授权

US09336897B2 Shift register circuit 有权
标题翻译：移位寄存器电路
公开(公告)号：US09336897B2
公开(公告)日：2016-05-10
申请号：US13455808
申请日：2012-04-25
申请人： Youichi Tobita , Isao Nojiri , Seiichiro Mori , Takashi Miyayama
发明人： Youichi Tobita , Isao Nojiri , Seiichiro Mori , Takashi Miyayama
IPC分类号： G11C19/00 , G11C19/28 , G09G3/36 , G11C19/18 , G09G3/32
CPC分类号： G11C19/28 , G09G3/3266 , G09G3/3677 , G09G2300/0408 , G09G2310/0286 , G09G2320/0233 , G11C19/184
摘要： A shift register circuit comprises a first transistor connected between a clock terminal and an output terminal, a second transistor for charging a control electrode of the first transistor in response to activation of an output signal of the preceding stage, a third transistor for discharging the control electrode of the first transistor, an inverter using a control electrode of the third transistor as an output end, and a fourth transistor which discharges an input end of the inverter at power-off and is turned off after power-on. A fifth transistor which is a load element of the inverter charges the control electrode of the third transistor at power-on. It is thereby possible to initialize the respective levels of the nodes without any external initialization signal and prevent a decrease in the level change rate of the output signal in the shift register circuit.
摘要翻译：移位寄存器电路包括连接在时钟端子和输出端子之间的第一晶体管，用于响应于前一级的输出信号的激活而对第一晶体管的控制电极进行充电的第二晶体管，用于对控制器进行放电的第三晶体管第一晶体管的电极，使用第三晶体管的控制电极作为输出端的反相器，以及在断电时对逆变器的输入端进行放电并在通电之后被截止的第四晶体管。作为逆变器的负载元件的第五晶体管在通电时对第三晶体管的控制电极进行充电。从而可以初始化节点的各个级别而没有任何外部初始化信号，并且防止移位寄存器电路中的输出信号的电平变化率的降低。

4. 发明申请

US20110142191A1 SHIFT REGISTER CIRCUIT 有权
标题翻译：移位寄存器电路
公开(公告)号：US20110142191A1
公开(公告)日：2011-06-16
申请号：US12951705
申请日：2010-11-22
申请人： Youichi TOBITA , Isao Nojiri , Seiichiro Mori , Takashi Miyayama
发明人： Youichi TOBITA , Isao Nojiri , Seiichiro Mori , Takashi Miyayama
IPC分类号： G11C19/00
CPC分类号： G11C19/28 , G09G3/3266 , G09G3/3677 , G09G2300/0408 , G09G2310/0286 , G09G2320/0233 , G11C19/184
摘要： A shift register circuit comprises a first transistor connected between a clock terminal and an output terminal, a second transistor for charging a control electrode of the first transistor in response to activation of an output signal of the preceding stage, a third transistor for discharging the control electrode of the first transistor, an inverter using a control electrode of the third transistor as an output end, and a fourth transistor which discharges an input end of the inverter at power-off and is turned off after power-on. A fifth transistor which is a load element of the inverter charges the control electrode of the third transistor at power-on. It is thereby possible to initialize the respective levels of the nodes without any external initialization signal and prevent a decrease in the level change rate of the output signal in the shift register circuit.
摘要翻译：移位寄存器电路包括连接在时钟端子和输出端子之间的第一晶体管，用于响应于前一级的输出信号的激活而对第一晶体管的控制电极进行充电的第二晶体管，用于对控制器进行放电的第三晶体管第一晶体管的电极，使用第三晶体管的控制电极作为输出端的反相器，以及在断电时对逆变器的输入端进行放电并在通电之后被截止的第四晶体管。作为逆变器的负载元件的第五晶体管在通电时对第三晶体管的控制电极进行充电。从而可以初始化节点的各个级别而没有任何外部初始化信号，并且防止移位寄存器电路中的输出信号的电平变化率的降低。

5. 发明授权

US08462285B2 Scanning line driving circuit for active matrix and image display device 有权
标题翻译：扫描线驱动电路用于有源矩阵和图像显示装置
公开(公告)号：US08462285B2
公开(公告)日：2013-06-11
申请号：US12342215
申请日：2008-12-23
申请人： Isao Nojiri , Hiroyuki Murai , Takashi Miyayama
发明人： Isao Nojiri , Hiroyuki Murai , Takashi Miyayama
IPC分类号： G02F1/136
CPC分类号： G02F1/13454
摘要： A first contact hole formed in a gate driving circuit is covered with an electrically conductive oxide film formed to be connected to the first contact hole and having a first pattern. The periphery of the electrically conductive oxide film is surrounded by an electrically conductive oxide film (a sacrifice electrode) formed simultaneously with the electrically conductive oxide film and having a second pattern form.
摘要翻译：形成在栅极驱动电路中的第一接触孔被形成为连接到第一接触孔并具有第一图案的导电氧化物膜覆盖。导电氧化物膜的周围由与导电氧化物膜同时形成并具有第二图案形式的导电氧化物膜（牺牲电极）包围。

6. 发明申请

US20090174695A1 SCANNING LINE DRIVING CIRCUIT FOR ACTIVE MATRIX AND IMAGE DISPLAY DEVICE 有权
标题翻译：用于主动矩阵和图像显示装置的扫描线驱动电路
公开(公告)号：US20090174695A1
公开(公告)日：2009-07-09
申请号：US12342215
申请日：2008-12-23
申请人： Isao Nojiri , Hiroyuki Murai , Takashi Miyayama
发明人： Isao Nojiri , Hiroyuki Murai , Takashi Miyayama
IPC分类号： G09G5/00
CPC分类号： G02F1/13454
摘要： A first contact hole formed in a gate driving circuit is covered with an electrically conductive oxide film formed to be connected to the first contact hole and having a first pattern. The periphery of the electrically conductive oxide film is surrounded by an electrically conductive oxide film (a sacrifice electrode) formed simultaneously with the electrically conductive oxide film and having a second pattern form.
摘要翻译：形成在栅极驱动电路中的第一接触孔被形成为连接到第一接触孔并具有第一图案的导电氧化物膜覆盖。导电氧化物膜的周围由与导电氧化物膜同时形成并具有第二图案形式的导电氧化物膜（牺牲电极）包围。

7. 发明申请

US20100289992A1 LIQUID CRYSTAL DISPLAY DEVICE 有权
标题翻译：液晶显示装置
公开(公告)号：US20100289992A1
公开(公告)日：2010-11-18
申请号：US12777541
申请日：2010-05-11
申请人： Isao Nojiri , Yasuo Fujita , Hiroyuki Murai
发明人： Isao Nojiri , Yasuo Fujita , Hiroyuki Murai
IPC分类号： G02F1/1343 , G02F1/1335
CPC分类号： G02F1/133512 , G02F1/13454 , G09G3/3674 , G09G2310/0286
摘要： Provided is a liquid crystal display device including contact hole parts in a gate line driving circuit, and light shielding layers formed of a metal material on a color filter substrate, where an insulating film is formed so as to cover the light shielding layer of the color filter substrate in a region on the array substrate, the area being opposed to the contact hole parts.
摘要翻译：提供一种液晶显示装置，其包括栅极线驱动电路中的接触孔部分和由滤色器基板上的金属材料形成的遮光层，其中形成绝缘膜以覆盖颜色的遮光层在阵列基板上的区域中的过滤器基板，该区域与接触孔部分相对。

8. 发明授权

US06985340B2 Semiconductor device with protection circuit protecting internal circuit from static electricity 有权
标题翻译：具有保护电路的半导体器件保护内部电路不受静电影响
公开(公告)号：US06985340B2
公开(公告)日：2006-01-10
申请号：US10648390
申请日：2003-08-27
申请人： Isao Nojiri , Hiroyuki Murai
发明人： Isao Nojiri , Hiroyuki Murai
IPC分类号： H02H3/22
CPC分类号： G09G3/006 , G02F1/136204 , H01L27/0255
摘要： A protection circuit described herein protects an LCD module from static electricity generated at a first positive power supply terminal in a process of manufacturing the LCD module. The protection circuit includes four diodes connected in series between a first node connected to the first positive power supply terminal and a second node receiving a reference potential, and a diode connected between the second and first nodes. When a first positive power supply voltage (10V) is applied to the first positive power supply terminal, the four diodes do not conduct. Therefore, a current consumption of the LCD module can accurately be measured.
摘要翻译：本文所述的保护电路在制造LCD模块的过程中保护LCD模块免受在第一正电源端子处产生的静电。保护电路包括串联连接在连接到第一正电源端子的第一节点和接收参考电位的第二节点之间的四个二极管以及连接在第二节点和第一节点之间的二极管。当第一正电源电压（10V）施加到第一正电源端子时，四个二极管不导通。因此，可以精确地测量LCD模块的电流消耗。

9. 发明申请

US20050179677A1 Image display apparatus having plurality of pixels arranged in rows and columns 有权
标题翻译：具有排列成行和列的多个像素的图像显示装置
公开(公告)号：US20050179677A1
公开(公告)日：2005-08-18
申请号：US11000241
申请日：2004-12-01
申请人： Isao Nojiri , Hiroyuki Murai
发明人： Isao Nojiri , Hiroyuki Murai
IPC分类号： G02F1/133 , G09G3/20 , G09G3/32 , G09G3/36
CPC分类号： G09G3/3677 , G09G3/3266 , G09G3/3275 , G09G3/3614 , G09G3/3618 , G09G3/3648 , G09G3/3688 , G09G2310/0289 , G09G2310/04
摘要： In a partial display mode, a source IC outputs a start signal at an “H” level designating the start of vertical scanning by a vertical scanning circuit, over a plurality of cycles from before a time T1 to after a time T8. A plurality of shift registers sequentially shift the start signal in synchronization with a clock signal to sequentially drive a plurality of activation enable signals, respectively, to an “H” level. Then, after time T8 when first to fourth activation enable signals simultaneously attain an “H” level, the source IC outputs an enabling signal at an “H” level to the vertical scanning circuit. In response, the vertical scanning circuit simultaneously activates first to fourth gate lines corresponding to the first to the fourth activation enable signals, respectively.
摘要翻译：在部分显示模式中，源IC在从时间T 1之前到时间T 8之后的多个周期中，通过垂直扫描电路输出指定垂直扫描开始的“H”电平的起始信号。多个移位寄存器顺序地将起始信号与时钟信号同步地移位，以分别将多个激活使能信号分别驱动到“H”电平。然后，在第一至第四激活使能信号同时达到“H”电平之后的时间T 8之后，源极IC向垂直扫描电路输出“H”电平的使能信号。作为响应，垂直扫描电路分别同时激活对应于第一至第四激活使能信号的第一至第四栅极线。

10. 发明授权

US06611468B2 Non-volatile semiconductor memory device having sensitive sense amplifier structure 失效
公开(公告)号：US06611468B2
公开(公告)日：2003-08-26
申请号：US09931759
申请日：2001-08-20
申请人： Isao Nojiri , Atsushi Ohba , Yoshihide Kai
发明人： Isao Nojiri , Atsushi Ohba , Yoshihide Kai
IPC分类号： G11C702
CPC分类号： G11C11/5642 , G11C16/28
摘要： In a non-volatile semiconductor memory device, a constant current circuit is arranged in parallel with an NMOS diode converting a detected current on the array cell side to a voltage, and a constant current circuit is arranged in parallel with an NMOS diode converting a detected current on the reference cell side to a voltage. Constant current circuits supply an offset current. Thus, a difference between two input voltages of a differential amplifier increases.

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