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1. 发明授权

US07315597B2 Sampling frequency conversion device and sampling frequency conversion method 有权
标题翻译：采样变频装置和采样频率转换方法
公开(公告)号：US07315597B2
公开(公告)日：2008-01-01
申请号：US10852236
申请日：2004-05-25
申请人： Yoshiyuki Tanaka , Yoshinari Ojima , Jun Wakasugi
发明人： Yoshiyuki Tanaka , Yoshinari Ojima , Jun Wakasugi
IPC分类号： H04L7/00
CPC分类号： H03H17/0628
摘要： A sampling frequency conversion device comprises an internal circuit for executing in synchronization with an internal clock a signal processing of input data fetched in accordance with an input word clock, and for outputting the input data having undergone the signal processing as output data, a clock generation circuit for generating from the internal clock an output word clock and a counter clock having a frequency which is equal to that of the output word clock multiplied by n (n: integer equal to two or more), a counter for counting the counter clock, and a register for holding a counter value of the counter in synchronization with the input word clock, and for outputting the held counter value to the internal circuit.
摘要翻译：采样频率转换装置包括内部电路，用于与内部时钟同步地执行根据输入字时钟获取的输入数据的信号处理，并且用于输出已经经过信号处理的输入数据作为输出数据，时钟产生用于从内部时钟产生输出字时钟和具有等于输出字时钟乘以n（n：等于2或更大的整数）的频率的计时器的计时器，用于计数计数器时钟的计数器，以及用于与输入字时钟同步地保持计数器的计数器值的寄存器，并且用于将保持的计数器值输出到内部电路。

2. 发明申请

US20050007863A1 Sampling frequency conversion device and sampling frequency conversion method 有权
标题翻译：采样变频装置和采样频率转换方法
公开(公告)号：US20050007863A1
公开(公告)日：2005-01-13
申请号：US10852236
申请日：2004-05-25
申请人： Yoshiyuki Tanaka , Yoshinari Ojima , Jun Wakasugi
发明人： Yoshiyuki Tanaka , Yoshinari Ojima , Jun Wakasugi
IPC分类号： H04B14/04 , G11C7/00 , H03H17/06 , H04L7/00
CPC分类号： H03H17/0628
摘要： A sampling frequency conversion device comprises an internal circuit for executing in synchronization with an internal clock a signal processing of input data fetched in accordance with an input word clock, and for outputting the input data having undergone the signal processing as output data, a clock generation circuit for generating from the internal clock an output word clock and a counter clock having a frequency which is equal to that of the output word clock multiplied by n (n: integer equal to two or more), a counter for counting the counter clock, and a register for holding a counter value of the counter in synchronization with the input word clock, and for outputting the held counter value to the internal circuit
摘要翻译：采样频率转换装置包括内部电路，用于与内部时钟同步地执行根据输入字时钟获取的输入数据的信号处理，并且用于输出已经经过信号处理的输入数据作为输出数据，时钟产生用于从内部时钟产生输出字时钟和具有等于输出字时钟乘以n（n：等于2或更大的整数）的频率的计时器的计时器，用于计数计数器时钟的计数器，以及用于与输入字时钟同步地保持计数器的计数器值的寄存器，并且用于将保持的计数器值输出到内部电路

3. 发明授权

US07134060B2 Semiconductor integrated circuit including operation test circuit and operation test method thereof 失效
标题翻译：半导体集成电路，包括操作测试电路及其运行测试方法
公开(公告)号：US07134060B2
公开(公告)日：2006-11-07
申请号：US10752504
申请日：2004-01-08
申请人： Yoshiyuki Tanaka , Yoshinari Ojima
发明人： Yoshiyuki Tanaka , Yoshinari Ojima
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/31727
摘要： A semiconductor integrated circuit disclosed herein comprising: a phase control circuit which shifts a phase of a first clock signal based on a phase control signal and outputs a second clock signal; a first flip-flop to which one of the first clock signal and the second clock signal is inputted as a first operation clock signal, and which outputs evaluation data; a circuit under test which performs a predetermined process based on the evaluation data and outputs a result of the process as output data; and a second flip-flop to which the other of the first clock signal and the second clock signal is inputted as a second operation clock signal and the output data is inputted, and which outputs the output data inputted from the circuit under test.
摘要翻译：本文公开的半导体集成电路包括：相位控制电路，其基于相位控制信号移位第一时钟信号的相位并输出第二时钟信号; 输入第一时钟信号和第二时钟信号中的一个作为第一操作时钟信号的第一触发器，并输出评估数据; 基于所述评价数据执行预定处理的输出电路，输出所述处理结果作为输出数据; 以及作为第二操作时钟信号输入第一时钟信号和第二时钟信号中的另一个的第二触发器，并输入输出数据，并输出从被测电路输入的输出数据。

4. 发明授权

US08897200B2 Relay system, relay device and synchronization method 有权
标题翻译：继电器系统，继电器和同步方式
公开(公告)号：US08897200B2
公开(公告)日：2014-11-25
申请号：US13121931
申请日：2009-10-28
申请人： Shoji Fukuzawa , Yoshiyuki Tanaka
发明人： Shoji Fukuzawa , Yoshiyuki Tanaka
IPC分类号： H04B7/14 , H04J1/10 , H04J3/08 , H04B7/155 , H04W24/04 , H04J3/06 , H04W88/08
CPC分类号： H04B7/155 , H04J3/0641 , H04W24/04 , H04W88/085
摘要： When no synchronization signal is transmitted over a system bus (115), a master repeater is arbitrarily selected from a plurality of repeaters (1112 to 111n), starts transmitting a synchronization signal over the system bus (115), and transmits information to the system bus (115) in synchronization with the synchronization signal. Other slave repeaters transmit information to the system bus (115) in synchronization with the synchronization signal transmitted by the master repeater.
摘要翻译：当没有通过系统总线（115）发送同步信号时，从多个中继器（1112至111n）中任意选择主中继器，开始通过系统总线（115）发送同步信号，并向系统发送信息总线（115）与同步信号同步。其他从属中继器与主中继器发送的同步信号同步地向系统总线（115）发送信息。

5. 发明授权

US08867429B2 Wireless communication system, wireless communication method thereof, repeater devices and wireless terminal devices 有权
标题翻译：无线通信系统，其无线通信方法，中继器设备和无线终端设备
公开(公告)号：US08867429B2
公开(公告)日：2014-10-21
申请号：US13121947
申请日：2009-10-28
申请人： Shoji Fukuzawa , Yoshiyuki Tanaka
发明人： Shoji Fukuzawa , Yoshiyuki Tanaka
IPC分类号： H04B7/14 , H04W48/20 , H04W72/04 , H04W88/08 , H04B7/26 , H04W48/08
CPC分类号： H04W48/20 , H04B7/2606 , H04W48/08 , H04W72/0493 , H04W88/08
摘要： Plural repeaters (1111 to 111n) are connected one another via a system bus (115), and each of which detects the state of another repeater by checking a signal transmitted over the system bus (115). When stopping the operation of home repeater (e.g., the repeater (1111)) which performs relaying process among wireless terminal devices (TA) to (TH), a secondary repeater (e.g., the repeater (1112)) set beforehand detects that the home repeater breaks down as the secondary repeater becomes unable to detect the signal over the system bus (115). The secondary repeater responds to the detection and bears the relaying process instead of the home repeater.
摘要翻译：多个中继器（1111至111n）经由系统总线（115）彼此连接，并且每个中继器通过检查通过系统总线（115）发送的信号来检测另一中继器的状态。当停止在无线终端装置（TA）至（TH）中执行中继处理的本地中继器（例如，中继器（1111））的操作时，预先设置的次级中继器（例如，中继器（1112））检测到家庭中继器因次级中继器无法通过系统总线（115）检测到信号而中断。次级中继器响应检测并承担中继过程，而不是本地中继器。

6. 发明授权

US08685350B2 Method for separating arsenic mineral from copper-bearing material with high arsenic grade 有权
标题翻译：从砷含量高的含砷材料中分离出砷矿物的方法
公开(公告)号：US08685350B2
公开(公告)日：2014-04-01
申请号：US13577353
申请日：2011-02-03
申请人： Hideyuki Okamoto , Yoshiyuki Tanaka , Tsuyoshi Hirajima , Keiko Sasaki
发明人： Hideyuki Okamoto , Yoshiyuki Tanaka , Tsuyoshi Hirajima , Keiko Sasaki
IPC分类号： B03D1/01
CPC分类号： C22B15/0008 , B03D1/01 , B03D1/016 , B03D2201/005 , B03D2201/06 , B03D2203/02
摘要： Disclosed herein is a method for separating an arsenic mineral from a copper-bearing material, including the steps of grinding a copper-bearing material containing arsenic, adding water to the copper-bearing material to prepare a slurry, and adding a flotation agent including a depressant, a frother, and a collector to the slurry and blowing air into the slurry for performing flotation to obtain a copper concentrate, wherein the depressant is a chelator. As the chelator, a polyethyleneamine or the like is used. Particularly, when triethylenetetramine is used as the chelator, the amount of triethylenetetramine to be added is preferably 1 to 10 equivalents relative to the amount of soluble copper generated by oxidation of the copper-bearing material, and the pH of the slurry is more preferably adjusted to 7 or more but 8 or less before the slurry is subjected to the flotation.
摘要翻译：本发明公开了一种从含铜材料中分离砷矿物的方法，包括以下步骤：研磨含有砷的含铜材料，向含铜材料中加入水以制备浆料，并加入浮选剂，包括抑制剂，起泡剂和收集剂，并将空气吹入浆料中进行浮选以获得铜精矿，其中抑制剂是螯合剂。作为螯合剂，使用聚乙烯胺等。特别是，当使用三亚乙基四胺作为螯合剂时，相对于通过含铜材料的氧化产生的可溶性铜的量，三亚乙基四胺的添加量优选为1〜10当量，更优选调节浆料的pH 在浆料进行浮选之前为7以上且8以下。

7. 发明授权

US08610351B2 Surge absorber 有权
标题翻译：浪涌吸收器
公开(公告)号：US08610351B2
公开(公告)日：2013-12-17
申请号：US13144599
申请日：2009-12-28
申请人： Yoshiyuki Tanaka , Tsuyoshi Ogi
发明人： Yoshiyuki Tanaka , Tsuyoshi Ogi
IPC分类号： H01J17/26 , H02H9/06
CPC分类号： H01T4/12 , H01T1/20
摘要： [Problems]Disclosed is a surge absorber which can absorb a surge having a long wave tail, wherein a stable sparkover voltage is obtained without applying a discharging aid to electrodes.[Means for Solving the Problems]The surge absorber is comprised of a pair of terminal electrode members (2) which are opposed to each other; and the insulation tube (3) on which the pair of terminal electrode members (2) are disposed on opposite ends thereof and that has a discharge control gas sealed therein. Bulging electrode elements (4) having an expanded center portion (4a) are formed on the inner surfaces of the terminal electrode members (2). The bulging electrode elements (4) contain metal which can emit more electrons than the terminal electrode members (2).
摘要翻译： [问题]公开了一种浪涌吸收器，其可以吸收具有长波尾的浪涌，其中在不向电极施加放电辅助的情况下获得稳定的火花放电电压。解决问题的手段浪涌吸收器由一对彼此相对的端子电极构件（2）构成; 以及绝缘管（3），其一对端子电极构件（2）在其两端设置并且具有密封在其中的排出控制气体。在端子电极构件（2）的内表面上形成具有扩大的中心部分（4a）的膨胀电极元件（4）。膨胀电极元件（4）包含能够比端子电极构件（2）发射更多的电子的金属。

8. 外观设计

USD685411S1 Printer 有权
公开(公告)号：USD685411S1
公开(公告)日：2013-07-02
申请号：US29419202
申请日：2012-04-26
申请人： Yoshiyuki Tanaka , Yuichi Kitazawa , Mugio Kawasaki , Seiji Kawabata , Koji Hara , Toshimitsu Ohara , Yoji Nakano
设计人： Yoshiyuki Tanaka , Yuichi Kitazawa , Mugio Kawasaki , Seiji Kawabata , Koji Hara , Toshimitsu Ohara , Yoji Nakano

9. 发明授权

US08397035B2 Semiconductor memory system with first and second nonvolatile memories storing user and management data and a controller controlling read/write of the memories and having simultaneous data transfer in and out of one of the memories 有权
标题翻译：具有存储用户和管理数据的第一和第二非易失性存储器的半导体存储器系统和控制存储器的读取/写入的控制器，并且具有同时进行数据传送进出存储器
公开(公告)号：US08397035B2
公开(公告)日：2013-03-12
申请号：US12945202
申请日：2010-11-12
申请人： Yoshiyuki Tanaka
发明人： Yoshiyuki Tanaka
IPC分类号： G06F13/00
CPC分类号： G06F12/0246 , G06F3/0611 , G06F3/0616 , G06F3/064 , G06F3/0679 , G06F3/0683 , G06F2212/7207 , G11C11/005 , G11C11/1657 , G11C11/1659 , G11C11/1675 , G11C16/102 , G11C2213/71 , Y02D10/13
摘要： A semiconductor storage device includes a first nonvolatile memory to store user data of a file, a second nonvolatile memory to store management data of the file, the second nonvolatile memory being different in type from the first nonvolatile memory, and a controller to control read/write of data with respect to the first and second nonvolatile memories.
摘要翻译：半导体存储装置包括存储文件的用户数据的第一非易失性存储器，存储文件的管理数据的第二非易失性存储器，与第一非易失性存储器不同类型的第二非易失性存储器，以及控制器，相对于第一和第二非易失性存储器写入数据。

10. 发明授权

US08008407B2 Process for preparing silicone polyethers 有权
标题翻译：硅氧烷聚醚的制备方法
公开(公告)号：US08008407B2
公开(公告)日：2011-08-30
申请号：US12294654
申请日：2007-03-29
申请人： Theodore Oberhellman , Yoshiyuki Tanaka , Charles Neal , Simon Parsley , Brian Deeth
发明人： Theodore Oberhellman , Yoshiyuki Tanaka , Charles Neal , Simon Parsley , Brian Deeth
IPC分类号： C08G77/12
CPC分类号： C08G77/46
摘要： A process is disclosed for the preparing silicone polyethers by reacting; (A) a polyether having at least one terminally unsaturated aliphatic hydrocarbon group and an alkali metal content of less than 50 ppm, (B) an organohydrogensiloxane having an acid number of less than 0.005, via a hydrosilylation reaction. The process is particularly useful to prepare silicone polyethers of improved quality via a continuous process.
摘要翻译：公开了通过反应制备硅氧烷聚醚的方法; （A）通过氢化硅烷化反应具有至少一个末端不饱和脂族烃基和碱金属含量小于50ppm的聚醚，（B）酸值小于0.005的有机氢硅氧烷。该方法通过连续方法制备具有改进质量的硅氧烷聚醚特别有用。

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