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1. 发明授权

US06346835B1 Power-on reset signal preparing circuit 有权
标题翻译：上电复位信号准备电路
公开(公告)号：US06346835B1
公开(公告)日：2002-02-12
申请号：US09538228
申请日：2000-03-30
申请人： Yoshitomo Ozeki , Hiroyuki Adachi
发明人： Yoshitomo Ozeki , Hiroyuki Adachi
IPC分类号： H03L700
CPC分类号： H03K5/153 , H03K17/223
摘要： A power-on reset signal preparing circuit including a pulse width preparing circuit for generating a pulse for resetting a main circuit based on a driving voltage output from a driving circuit based on the output voltages from two charging circuits with different charging times. The driving circuit may be a switching circuit utilizing charged potential difference of the two charging circuits, a gate circuit utilizing a charging time difference of the two charging circuits, or a differential transistor pair utilizing the charging potential difference or time difference of the two charging circuits. The pulse width preparing circuit may be formed by two wiring lines, connected between the output of the driving circuit and the ground and running substantially parallel to each other, whereby the capacitors may be small in size.
摘要翻译：一种上电复位信号准备电路，包括：脉冲宽度准备电路，用于基于来自具有不同充电时间的两个充电电路的输出电压，基于从驱动电路输出的驱动电压产生用于复位主电路的脉冲。驱动电路可以是使用两个充电电路的充电电位差的开关电路，利用两个充电电路的充电时间差的门电路或利用两个充电电路的充电电位差或时间差的差分晶体管对。脉冲宽度准备电路可以由连接在驱动电路的输出端和地之间的两条布线形成，并且基本上彼此平行地延伸，由此电容器的尺寸可能较小。

2. 发明申请

US20050146378A1 Voltage stabilizer 有权
标题翻译：稳压器
公开(公告)号：US20050146378A1
公开(公告)日：2005-07-07
申请号：US11068761
申请日：2005-03-02
申请人： Yoshitomo Ozeki , Hisashige Ando
发明人： Yoshitomo Ozeki , Hisashige Ando
IPC分类号： G05F1/613 , G05F1/10
CPC分类号： G05F1/613
摘要： The present invention relates to a voltage stabilizer that stabilizes the voltage of a power supply line on a semiconductor substrate and is intended to provide a voltage stabilizer having a small mounting area on the semiconductor substrate, capable of stabilizing the voltage of the power supply path connecting the power supply and semiconductor substrate. The voltage stabilizer includes a monitoring section 110 connected to the power supply line Vdd that monitors the potential of the power supply line Vdd and outputs a monitor signal indicating the monitoring result and a first current control section 120 that passes a current from the power supply line Vdd according to the monitor signal to stabilize the voltage of the power supply line Vdd, capable of freely passing a current continuously.
摘要翻译：本发明涉及稳定半导体基板上的电源线的电压的稳压器，旨在提供一种在半导体基板上具有小安装面积的稳压器，能够稳定连接电源的路径的电压电源和半导体基板。电压稳定器包括连接到电源线Vdd的监视部分110，其监视电源线Vdd的电位并输出指示监视结果的监视信号;以及第一电流控制部分120，其将来自电源线的电流 Vdd根据监视信号稳定电源线Vdd的电压，能够连续自由地通过电流。

3. 发明授权

US08427208B2 Phase interpolator and semiconductor circuit device 失效
标题翻译：相位内插器和半导体电路器件
公开(公告)号：US08427208B2
公开(公告)日：2013-04-23
申请号：US13369847
申请日：2012-02-09
申请人： Yoshitomo Ozeki
发明人： Yoshitomo Ozeki
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03K5/13 , H03K2005/00052 , H03K2005/00156 , H03K2005/00195 , H03K2005/00286 , H03L7/087 , H04L7/0025 , H04L7/0337
摘要： A first mixer generates a first and a second clock signal having a phase opposite to that of the first clock signal. A second mixer generates a third clock signal having a phase lead angle of 90 degrees with respect to the first clock signal and a fourth clock signal having a phase opposite to that of the third clock signal. An ADC generates a digital signal from a signal that is generated on the basis of a composite signal of a voltage signal formed on the basis of the exclusive OR of the first and the third clock signal and a voltage signal formed on the basis of the exclusive OR of the second and the fourth clock signal. An adder adds the digital signal to the first control signal to generate the second control signal and supplies the second control signal to the second mixer.
摘要翻译：第一混频器产生具有与第一时钟信号的相位相反的相位的第一和第二时钟信号。第二混频器产生相对于第一时钟信号具有90度的相位超前角的第三时钟信号和具有与第三时钟信号的相位相反的相位的第四时钟信号。 ADC从根据基于第一和第三时钟信号的异或形成的电压信号的复合信号和基于排他性形成的电压信号产生的信号产生数字信号或第二和第四个时钟信号。加法器将数字信号与第一控制信号相加以产生第二控制信号，并将第二控制信号提供给第二混频器。

4. 发明授权

US08793297B2 Phase interpolator, semiconductor device and testing method thereof 有权
标题翻译：相位内插器，半导体器件及其测试方法
公开(公告)号：US08793297B2
公开(公告)日：2014-07-29
申请号：US13356788
申请日：2012-01-24
申请人： Yoshitomo Ozeki
发明人： Yoshitomo Ozeki
IPC分类号： G06F17/17 , G01R31/317
CPC分类号： G01R31/31726
摘要： Two selected testing selectors output testing input signals of reverse phases from each other according to the first control signal. Two selectors corresponding to the two testing selectors output the testing input signals output from the two testing selectors according to the second control signal. Two mixers corresponding to the two selectors output an output signal in which weighting is added to the testing input signals output from the two selectors are compounded. A detection circuit outputs an error signal when the output signal output from the two mixers is larger than a threshold value.
摘要翻译：两个选择的测试选择器根据第一控制信号输出相反相的测试输入信号。对应于两个测试选择器的两个选择器根据第二控制信号输出从两个测试选择器输出的测试输入信号。对应于两个选择器的两个混频器输出一个输出信号，其中加权加到从两个选择器输出的测试输入信号中。当从两个混频器输出的输出信号大于阈值时，检测电路输出误差信号。

5. 发明授权

US07038529B2 Voltage stabilizer 有权
标题翻译：稳压器
公开(公告)号：US07038529B2
公开(公告)日：2006-05-02
申请号：US11068761
申请日：2005-03-02
申请人： Yoshitomo Ozeki , Hisashige Ando
发明人： Yoshitomo Ozeki , Hisashige Ando
IPC分类号： G05F1/10
CPC分类号： G05F1/613
摘要： The present invention relates to a voltage stabilizer that stabilizes the voltage of a power supply line on a semiconductor substrate and is intended to provide a voltage stabilizer having a small mounting area on the semiconductor substrate, capable of stabilizing the voltage of the power supply path connecting the power supply and semiconductor substrate. The voltage stabilizer includes a monitoring section 110 connected to the power supply line Vdd that monitors the potential of the power supply line Vdd and outputs a monitor signal indicating the monitoring result and a first current control section 120 that passes a current from the power supply line Vdd according to the monitor signal to stabilize the voltage of the power supply line Vdd, capable of freely passing a current continuously.
摘要翻译：本发明涉及稳定半导体基板上的电源线的电压的稳压器，旨在提供一种在半导体基板上具有小安装面积的稳压器，能够稳定连接电源的路径的电压电源和半导体基板。电压稳定器包括连接到电源线Vdd的监视部分110，其监视电源线Vdd的电位并输出指示监视结果的监视信号;以及第一电流控制部分120，其将来自电源线的电流 Vdd根据监视信号稳定电源线Vdd的电压，能够连续自由地通过电流。

6. 发明授权

US06847222B2 Apparatus for measuring voltage fluctuation waveform in semiconductor integrated circuit, and semiconductor integrated circuit having function for measuring voltage fluctuation waveform 失效
标题翻译：用于测量半导体集成电路中的电压波动波形的装置，以及具有用于测量电压波动波形的功能的半导体集成电路
公开(公告)号：US06847222B2
公开(公告)日：2005-01-25
申请号：US10780610
申请日：2004-02-19
申请人： Keisuke Muraya , Yoshitomo Ozeki
发明人： Keisuke Muraya , Yoshitomo Ozeki
IPC分类号： G01R31/28 , G01R19/165 , G01R31/02 , H01L21/66 , H01L21/82 , H02M3/335
CPC分类号： G01R19/16519 , G01R31/2884
摘要： An apparatus measures a voltage fluctuation waveform in a semiconductor integrated circuit having a large number of wiring layers and being operated on a lower voltage without a destructive inspection. For this propose, the apparatus includes a power-source-system waveform converting circuit, disposed close to a functional circuit and in the LSI and operated on a second rated voltage higher than a first rated voltage, for converting the voltage fluctuation waveform of the power source system into an electrical current waveform; a pad for outputting the electric current waveform outside the LSI; and a wiring, arranged in the LSI, for connecting the power-source-system waveform converting circuit and the pad. The apparatus is used to measure a voltage fluctuation waveform near a particular circuit in operation included in, for example, a CMOS LSI.
摘要翻译：一种装置测量具有大量布线层的半导体集成电路中的电压波动波形，并且在没有破坏性检查的情况下以较低电压运行。为此，该装置包括电源系统波形转换电路，该电源系统波形转换电路设置在功能电路附近并且在LSI中并且以高于第一额定电压的第二额定电压进行操作，用于将电力的电压波动波形源系统变成电流波形; 用于在LSI外部输出电流波形的焊盘; 和布置在LSI中的用于连接电源系统波形转换电路和焊盘的布线。该装置用于测量包括在例如CMOS LSI中的操作中的特定电路附近的电压波动波形。

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