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1. 发明授权

US08645759B2 Debugging mechanism having an OR circuit for triggering storage of arithmetic operation data whenever a valid control signal is received or a clock-based counter overflows 失效
标题翻译：调试机制具有OR电路，用于每当接收到有效控制信号或基于时钟的计数器溢出时触发算术运算数据的存储
公开(公告)号：US08645759B2
公开(公告)日：2014-02-04
申请号：US12198704
申请日：2008-08-26
申请人： Yoshiteru Ohnuki , Hideo Yamashita
发明人： Yoshiteru Ohnuki , Hideo Yamashita
IPC分类号： G06F11/34 , G06F17/40
CPC分类号： G06F11/3648 , G06F11/3656
摘要： A debugging mechanism receives arithmetic operation data inputs for causing an arithmetic unit to perform an arithmetic operation, and a control signal used for the arithmetic operation. The debugging mechanism includes a debug control unit which includes (1) a counter that performs a counting operation cyclically according to the processor clock operation, and (2) an OR circuit that receives the control signal and a counter signal that is output when the counter value becomes a specific value, and outputs an output signal generated by performing a logical OR operation of the control signal and the counter signal. The debugging mechanism also includes a debug storage unit which stores the arithmetic operation data, the counter value, and the control signal when the output of the OR circuit is valid.
摘要翻译：调试机构接收用于使算术单元执行算术运算的算术运算数据输入，以及用于算术运算的控制信号。调试机构包括调试控制单元，其包括：（1）根据处理器时钟操作循环执行计数操作的计数器，以及（2）接收控制信号的OR电路和当计数器输出时输出的计数器信号值变为特定值，并且输出通过执行控制信号和计数器信号的逻辑或运算而产生的输出信号。调试机构还包括调试存储单元，其在OR电路的输出有效时存储算术运算数据，计数器值和控制信号。

2. 发明授权

US08732550B2 Processor and error correcting method 有权
标题翻译：处理器和纠错方法
公开(公告)号：US08732550B2
公开(公告)日：2014-05-20
申请号：US12633079
申请日：2009-12-08
申请人： Yoshiteru Ohnuki , Hideo Yamashita
发明人： Yoshiteru Ohnuki , Hideo Yamashita
IPC分类号： G06F11/00
CPC分类号： G06F11/1008 , G06F9/30105 , G06F9/30138 , G06F9/3865 , G06F11/1076 , G06F2211/109
摘要： A processor for processing data and correcting an error occurring in the data, the processor includes: a register that stores data with error check data and error correction data; an error detector that detects an error in the data stored in the register by using the error check data; and an error corrector that corrects the detected error by using the error correction data and that stores the corrected data back into the register.
摘要翻译：一种用于处理数据并纠正数据中发生的错误的处理器，所述处理器包括：存储具有错误校验数据和纠错数据的数据的寄存器; 错误检测器，通过使用错误检查数据来检测存储在寄存器中的数据的错误; 以及错误校正器，其通过使用纠错数据来校正检测到的错误，并将校正的数据存储回寄存器。

3. 发明授权

US08539208B2 Register file having multiple windows and a current window pointer 有权
标题翻译：具有多个窗口和当前窗口指针的注册文件
公开(公告)号：US08539208B2
公开(公告)日：2013-09-17
申请号：US13017665
申请日：2011-01-31
申请人： Yoshiteru Ohnuki
发明人： Yoshiteru Ohnuki
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/30127 , G06F9/30141
摘要： In an arithmetic processing unit adopting register windows, a configuration is made such that the reading process of a register file is controlled by two stages of a current window selection and a register selection, and the register selected at a plurality of reading ports of the register is set to each port in advance such that it will be out-of-order executable. Accordingly, the process of reading the data into an arithmetic section is possible without having a temporary memory, and an instruction subsequent to a window switching instruction is also out-of-order executable.
摘要翻译：在采用寄存器窗口的算术处理单元中，进行配置，使得寄存器文件的读取处理由当前窗口选择和寄存器选择的两个阶段控制，并且在寄存器的多个读取端口处选择的寄存器被预先设置到每个端口，使得它将是无序可执行的。因此，可以在不具有临时存储器的情况下读取数据到算术部分的处理，并且窗口切换指令之后的指令也是无序可执行的。

4. 发明授权

US08448019B2 Processor, information processing apparatus, and method of controlling processor 失效
标题翻译：处理器，信息处理装置和控制处理器的方法
公开(公告)号：US08448019B2
公开(公告)日：2013-05-21
申请号：US12971949
申请日：2010-12-17
申请人： Yoshiteru Ohnuki , Norihito Gomyo
发明人： Yoshiteru Ohnuki , Norihito Gomyo
IPC分类号： G06F11/00
CPC分类号： G06F11/1048
摘要： A processor includes an accumulator, a storage that outputs data to the accumulator, an error detector that outputs a first error detection signal upon detecting an error in the data, an error identifier that outputs an error identification signal indicating that an error occurs in the storage, an error identification signal holder that outputs the error identification signal as a second error detection signal, an error detection signal holder that holds the first error detection signal and outputs a cancellation signal to stop the accumulation processing of the accumulator, a first calculator that starts making a first calculation based on the second error detection signal and the cancellation signal, and outputs a correction start signal after a lapse of a calculation period, and an error corrector that corrects the error of the data upon receiving the correction start signal.
摘要翻译：处理器包括累加器，向累加器输出数据的存储器，检测到数据中的错误时输出第一错误检测信号的错误检测器，输出指示存储器中发生错误的错误识别信号的错误标识符输出作为第二误差检测信号的误差识别信号的误差识别信号保持器，保持第一误差检测信号并输出消除信号以停止累加器的累积处理的误差检测信号保持器，启动的第一计算器基于第二错误检测信号和消除信号进行第一次计算，并且在经过计算周期之后输出校正开始信号;以及纠错器，其在接收到校正开始信号时校正数据的误差。

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