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    • 4. 发明授权
    • Reception apparatus
    • 接收设备
    • US08098786B2
    • 2012-01-17
    • US12594915
    • 2008-02-08
    • Kazuyuki OmoteRyutaro Saito
    • Kazuyuki OmoteRyutaro Saito
    • H04L7/00
    • H03L7/07H03L7/0812H04L7/0008H04L7/0337
    • In a reception apparatus 1, a multiphase sampling clock signal is generated by a sampling clock signal generation circuit 40, based on a clock signal which has been phase-adjusted by a phase adjustment circuit 50. The data of each of the bits of a serial data signal is sampled and output by a sampler block circuit 30n, with timing indicated by the sampling clock signal. The amount of phase adjustment of the clock signal in the phase adjustment circuit 50 is set such that the delay time from generation of the multiphase sampling clock signal in the sampling clock signal generation circuit 40 until indication of the sampling timing by the sampling clock signal in the sampler block circuit 30n is canceled.
    • 在接收装置1中,基于由相位调整电路50进行相位调整的时钟信号,由采样时钟信号生成电路40生成多相采样时钟信号。串行的每个位的数据 数据信号由采样器块电路30n采样并由采样时钟信号指示定时。 相位调整电路50中的时钟信号的相位调整量被设定为使得在采样时钟信号发生电路40中产生多相采样时钟信号的延迟时间直到通过采样时钟信号的采样定时指示 取样器块电路30n被取消。
    • 5. 发明申请
    • RECEPTION APPARATUS
    • 接收装置
    • US20100119023A1
    • 2010-05-13
    • US12594915
    • 2008-02-08
    • Kazuyuki OmoteRyutaro Saito
    • Kazuyuki OmoteRyutaro Saito
    • H04L7/00
    • H03L7/07H03L7/0812H04L7/0008H04L7/0337
    • In a reception apparatus 1, a multiphase sampling clock signal is generated by a sampling clock signal generation circuit 40, based on a clock signal which has been phase-adjusted by a phase adjustment circuit 50. The data of each of the bits of a serial data signal is sampled and output by a sampler block circuit 30n, with timing indicated by the sampling clock signal. The amount of phase adjustment of the clock signal in the phase adjustment circuit 50 is set such that the delay time from generation of the multiphase sampling clock signal in the sampling clock signal generation circuit 40 until indication of the sampling timing by the sampling clock signal in the sampler block circuit 30n is canceled.
    • 在接收装置1中,基于由相位调整电路50进行相位调整的时钟信号,由采样时钟信号生成电路40生成多相采样时钟信号。串行的每个位的数据 数据信号由采样器块电路30n采样并由采样时钟信号指示定时。 相位调整电路50中的时钟信号的相位调整量被设定为使得在采样时钟信号发生电路40中产生多相采样时钟信号的延迟时间直到通过采样时钟信号的采样定时指示 取样器块电路30n被取消。