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1. 发明申请

US20120020257A1 WIRELESS COMMUNICATION APPARATUS AND WIRELESS COMMUNICATION METHOD 有权
标题翻译：无线通信设备和无线通信方法
公开(公告)号：US20120020257A1
公开(公告)日：2012-01-26
申请号：US13233310
申请日：2011-09-15
申请人： Yoshio URABE , Kenji MIYANAGA , Kazuhiro ANDO , Chalermphol APICHAICHALERMWONGSE , Tsutomu MUKAI
发明人： Yoshio URABE , Kenji MIYANAGA , Kazuhiro ANDO , Chalermphol APICHAICHALERMWONGSE , Tsutomu MUKAI
IPC分类号： H04W52/04 , H04W4/00
CPC分类号： H04W74/0808 , H04W56/002 , H04W72/1205
摘要： When communicating with a second wireless station, a first wireless station judges, based on link-related information received from the second wireless station and link-related information extracted from a signal transmitted by a fourth wireless station, whether a transmission link from the third wireless station to the fourth wireless station and a transmission link from the first wireless station to the second wireless station can be concurrently established without interference with each other. If judging affirmatively, the first wireless station transmits a signal to the second wireless station in synchronization with a signal transmitted by the third wireless station to the fourth wireless station.
摘要翻译：当与第二无线站通信时，第一无线站基于从第二无线站接收到的链路相关信息和从由第四无线站发送的信号中提取的链路相关信息来判断来自第三无线站的传输链路可以同时建立到第四无线站的站和从第一无线站到第二无线站的传输链路，而不会彼此干扰。如果肯定地判断，则第一无线站与第三无线站向第四无线站发送的信号同步地向第二无线站发送信号。

2. 发明申请

US20110025424A1 PLL/FLL CIRCUIT WITH GAIN CONTROL 有权
标题翻译：具有增益控制的PLL / FLL电路
公开(公告)号：US20110025424A1
公开(公告)日：2011-02-03
申请号：US12534663
申请日：2009-08-03
申请人： Kenji MIYANAGA
发明人： Kenji MIYANAGA
IPC分类号： H03L7/08
CPC分类号： H03L7/093 , H03C3/0941 , H03C3/095 , H03C3/0966
摘要： An FLL circuit having a capability of configuring a desired loop bandwidth in a short period of time is provided. An FDC 17 generates a feedback of an output signal of a VCO 15. An error detector 11 detects an error of the output signal of the VCO 15. A voltage retainer 13 retains an output of a control voltage of the VCO 15. A reference signal generator 16 generates a reference signal. An adder 14 adds the reference signal to a control voltage outputted by the voltage retainer 13. A Kv calculator 18 calculates a gain Kv of the VCO 15 based on a degree of transition of an output frequency of the VCO 15. A loop bandwidth controller 19 adjusts, based on the gain Kv of the VCO 15, a gain of a loop filter 12 to an optimum value, and configures a desired loop bandwidth.
摘要翻译：提供了具有在短时间内配置期望的环路带宽的能力的FLL电路。 FDC17产生VCO15的输出信号的反馈。误差检测器11检测VCO15的输出信号的误差。电压保持器13保持VCO15的控制电压的输出。参考信号发生器16产生参考信号。加法器14将参考信号与由电压保持器13输出的控制电压相加.Kv计算器18基于VCO15的输出频率的转变程度来计算VCO 15的增益Kv。环路带宽控制器19 基于VCO15的增益Kv将环路滤波器12的增益调整到最佳值，并且配置期望的环路带宽。

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