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    • 1. 发明授权
    • Method for inspecting semiconductor devices
    • 检测半导体器件的方法
    • US5321354A
    • 1994-06-14
    • US842121
    • 1992-05-18
    • Yoshimasa OoshimaToshio ShimizuKatsuya IidaFumiaki Kumazawa
    • Yoshimasa OoshimaToshio ShimizuKatsuya IidaFumiaki Kumazawa
    • G01R31/28G01R31/30G06F11/22H01L21/66
    • G06F11/2273G01R31/3004
    • A method for detecting the quality of a semiconductor device using a static current that flows in a state wherein internal elements are fixed, the semiconductor device has internal elements, such as MISFETs and complementary MISFETs in particular. By using a pattern group that controls the state of nodes of the internal elements or ON/OFF and other states of MISFETs that comprise the internal elements, as a test pattern group used for this inspection, faults involving long range reliability in addition to degenerate faults and those faults detected using conventional fault simulation may be detected. In the inspection method based on static current, observability of faults at output terminals need not be taken into consideration, so that the number of patterns in the test pattern group used for inspection may be less and may be easily created.
    • PCT No.PCT / JP91 / 00971 Sec。 371日期:1992年5月18日 102(e)日期1992年5月18日PCT提交1991年7月9日PCT公布。 第WO92 / 01942号公报 日期:1992年2月6日。一种用于使用在内部元件固定的状态下流动的静电流来检测半导体器件的质量的方法,该半导体器件具有诸如MISFET和互补MISFET的内部元件。 通过使用控制内部元件的节点状态的图案组或ON / OFF以及包含内部元件的MISFET的其他状态,作为用于该检查的测试图案组,除了退化故障之外还涉及长距离可靠性 并且可以检测使用常规故障模拟检测到的那些故障。 在基于静态电流的检查方法中,不需要考虑输出端子故障的可观察性,因此用于检查的测试图案组中的图案数量可能较少,可能容易创建。
    • 2. 发明授权
    • Method and system for inspecting electronic circuit pattern
    • 检查电路图的方法和系统
    • US07231079B2
    • 2007-06-12
    • US10050519
    • 2002-01-18
    • Hirohito OkudaYuji TakagiMasahiro WatanabeShunji MaedaMinori NoguchiYoshimasa OoshimaMakoto Ono
    • Hirohito OkudaYuji TakagiMasahiro WatanabeShunji MaedaMinori NoguchiYoshimasa OoshimaMakoto Ono
    • G06K9/00
    • G01N21/956G01N21/9501G01N2021/8854G01N2021/8861
    • For the purpose of reducing a false report and shortening inspection time, an area to be inspected is locally inspected under optimum inspection conditions. In order to avoid the number of detected defects from increasing explosively, and thereby to facilitate control of a critical defect, general-purpose layout data, which is used for producing a mask of a semiconductor wafer, is accumulated in a design information server 2. With reference to the layout data, an area to be inspected, which is inspected by a pattern inspecting apparatus 1, is divided into partial inspection areas including a cell portion and a non-cell portion. Inspection parameters are set for each of the partial inspection areas. In addition, the defect reviewing apparatus 8 obtains an inspection result of the pattern inspecting apparatus 1. When obtaining a defect image, the defect reviewing apparatus 8 identifies a position, where the defect occurred, from among a cell portion, a non-cell portion, a pattern dense portion, and the like according to layout data. Moreover, the defect reviewing apparatus 8 sets inspection parameters, such as pickup magnification of this defect, in response to a result of the identification to set a control criterion of criticality.
    • 为了减少虚假报告和缩短检查时间,在最佳检查条件下对被检查区域进行局部检查。 为了避免检测到的缺陷数量爆炸性增加,从而有利于控制关键缺陷,用于制造半导体晶片的掩模的通用布局数据被累积在设计信息服务器2中。 参照布局数据,由图案检查装置1检查的被检查区域被划分为包括单元部分和非单元部分的局部检查区域。 为每个部分检查区域设置检查参数。 另外,缺陷检查装置8获得图案检查装置1的检查结果。 当获得缺陷图像时,缺陷检查装置8根据布局数据从单元部分,非单元部分,图案密集部分等中识别发生缺陷的位置。 此外,缺陷检查装置8响应于识别的结果设置检查参数,例如该缺陷的拾取倍率,以设置关键性的控制标准。