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    • 5. 发明申请
    • POWER CONVERSION APPARATUS
    • 功率转换装置
    • US20130121045A1
    • 2013-05-16
    • US13699815
    • 2010-10-26
    • Satoshi MurakamiMasaki YamadaTakashi KaneyamaKazutoshi Awane
    • Satoshi MurakamiMasaki YamadaTakashi KaneyamaKazutoshi Awane
    • H02M7/219
    • H02M7/219H02M7/49H02M2007/4835
    • An inverter circuit is connected in series to an AC power supply, and at the subsequent stage, a smoothing capacitor is connected via a converter circuit including semiconductor switching devices. A control circuit controls the converter circuit by providing a short-circuit period for bypassing the smoothing capacitor in each cycle, and controls the inverter circuit to improve the power factor of the AC power supply by using a current instruction such that the voltage of the smoothing capacitor becomes a target voltage. When the voltage of a DC voltage source of the inverter circuit has exceeded a predetermined upper limit, the control circuit increases the current instruction to control the inverter circuit, thereby increasing the discharge amount of the DC voltage source. Thus, even if the voltage variation of the DC voltage source of the inverter circuit increases, it is possible to stably continue the control.
    • 逆变器电路与AC电源串联连接,在后续阶段,通过包括半导体开关器件的转换器电路连接平滑电容器。 控制电路通过在每个周期中提供用于旁路平滑电容器的短路周期来控制转换器电路,并且通过使用电流指令来控制逆变器电路来提高交流电源的功率因数,使得平滑电压 电容器成为目标电压。 当逆变器电路的直流电压源的电压超过预定的上限时,控制电路增加用于控制逆变器电路的电流指令,从而增加直流电压源的放电量。 因此,即使逆变器电路的直流电压源的电压变化增大,也可以稳定地进行控制。
    • 7. 再颁专利
    • Semiconductor device and manufacturing method thereof
    • 半导体装置及其制造方法
    • USRE43320E1
    • 2012-04-24
    • US12202037
    • 2008-08-29
    • Masaki YamadaHideki Shibata
    • Masaki YamadaHideki Shibata
    • H01L29/40H01L23/48H01L23/52
    • H01L23/53238H01L23/53295H01L2924/0002H01L2924/00
    • There is disclosed a semiconductor device comprising a first metal wiring buried in a first wiring groove formed, via a first barrier metal, in a first insulating layer formed on a semiconductor substrate, a second insulating layer formed on the first metal wiring, a via plug formed of a metal buried, via a second barrier metal, in a via hole formed in the second insulating layer, a third insulating layer formed on the second insulating layer in which the via plug is buried, and a second metal wiring buried in a second wiring groove formed in the third insulating layer via a third barrier metal having a layer thickness of layer quality different from that of the second barrier metal.
    • 公开了一种半导体器件,其包括埋在第一布线槽中的第一金属布线,第一布线槽经由第一阻挡金属形成在形成于半导体基板上的第一绝缘层中,形成在第一金属布线上的第二绝缘层, 由形成在所述第二绝缘层中的通孔中的通过第二阻挡金属掩埋的金属形成,形成在所述第二绝缘层上的第三绝缘层,所述第二绝缘层中埋设有所述通孔插塞,以及第二金属布线, 通过具有不同于第二阻挡金属的层质量的层厚度的第三阻挡金属形成在第三绝缘层中的布线槽。