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1. 发明申请

US20130157437A1 PATTERN FORMING METHOD 有权
标题翻译：图案形成方法
公开(公告)号：US20130157437A1
公开(公告)日：2013-06-20
申请号：US13601003
申请日：2012-08-31
申请人： Yoshihiro YANAI , Koichi MATSUNO , Seiro MIYOSHI
发明人： Yoshihiro YANAI , Koichi MATSUNO , Seiro MIYOSHI
IPC分类号： H01L21/302 , H01L21/76
CPC分类号： H01L21/0274 , G11C16/0408 , H01L21/0337 , H01L21/28123 , H01L21/32139 , H01L27/11524 , H01L29/66825
摘要： According to one embodiment, firstly, an inversion pattern having a periodic pattern in which a first line pattern and a space are inversed and a non-periodic pattern arranged at an interval which is substantially equal to the width of the first line pattern from the end of the periodic pattern is formed above a processing object so as to correspond to the plurality of spaces between a plurality of first line patterns in a first pattern and the space between the first pattern and a second pattern. Next, a sidewall film is formed around the inversion pattern, and the periodic pattern is removed selectively. Thereafter, the processing object is etched using the sidewall pattern formed of the sidewall film and the non-periodic pattern surrounded by the sidewall film as masks.
摘要翻译：根据一个实施例，首先，具有其中第一线图案和空间被倒置的周期性图案的反转图案和以从第一个第一线图案的宽度基本上等于第一线图案的宽度的间隔排列的非周期性图案在处理对象之上形成周期性图案，以便对应于第一图案中的多个第一线图案与第一图案与第二图案之间的空间之间的多个间隔。接下来，在反转图案周围形成侧壁膜，并且选择性地去除周期性图案。此后，使用由侧壁膜形成的侧壁图案和由侧壁膜包围的非周期性图案作为掩模来蚀刻处理对象。

2. 发明申请

US20080315325A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080315325A1
公开(公告)日：2008-12-25
申请号：US12142326
申请日：2008-06-19
申请人： Koichi MATSUNO
发明人： Koichi MATSUNO
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7833 , H01L27/115 , H01L29/6659
摘要： A semiconductor device including a semiconductor substrate; an element isolation region formed in the substrate including trenches formed at a first depth and being filled with an element isolation insulating film; an element forming region formed on the substrate and being surrounded by the trenches; a gate electrode formed along a first direction on the element forming region via a gate insulating film, the gate electrode extending over the element insulating film filled the trenches extending along a second direction; a source/drain region having a second depth less than the first depth formed in the element forming region beside the gate electrode and having an exposed surface exposed to a trench sidewall; wherein the upper surface of the element isolation insulating film exclusive of a portion underlying the gate electrode is located at a third depth greater than the second depth and less than the first depth.
摘要翻译：一种半导体器件，包括半导体衬底; 形成在所述基板中的元件隔离区域，所述元件隔离区域包括形成在第一深度并且填充有元件隔离绝缘膜的沟槽; 元件形成区域，形成在所述基板上并被所述沟槽包围; 经由栅极绝缘膜沿元件形成区域沿着第一方向形成的栅电极，在所述元件绝缘膜上延伸的所述栅电极填充沿着第二方向延伸的沟槽; 源极/漏极区域，具有小于在栅电极旁边的元件形成区域中形成的第一深度的第二深度，并且具有暴露于沟槽侧壁的暴露表面; 其中所述元件隔离绝缘膜的除了所述栅电极下方的部分的上表面位于大于所述第二深度且小于所述第一深度的第三深度。

3. 发明申请

US20130252388A1 METHOD OF MANUFACTURING NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：制造非易失性半导体存储器件的方法
公开(公告)号：US20130252388A1
公开(公告)日：2013-09-26
申请号：US13598983
申请日：2012-08-30
申请人： Koichi MATSUNO
发明人： Koichi MATSUNO
IPC分类号： H01L29/66
CPC分类号： H01L29/66825 , H01L21/764 , H01L27/11524 , H01L29/7881
摘要： A method of manufacturing a non-volatile semiconductor memory device of an embodiment includes: forming, on a semiconductor substrate, an element isolation region to be filled with a first insulating film; forming memory cell gate electrodes on element regions; etching the first insulating film so that the first insulating film remains in the element isolation region of a region in which a select gate electrode is to be formed; forming a second insulating film on the memory cell gate electrodes so that an air gap is created between the memory cell gate electrodes; forming two select gate electrodes; forming carbon side walls on the select gate electrodes; implanting ions of an impurity between the two select gate electrodes with the side walls as a mask; and removing the carbon side walls.
摘要翻译：制造实施例的非易失性半导体存储器件的方法包括：在半导体衬底上形成待填充第一绝缘膜的元件隔离区; 在元件区域上形成存储单元栅电极; 蚀刻第一绝缘膜，使得第一绝缘膜保留在要形成选择栅电极的区域的元件隔离区域中; 在所述存储单元栅电极上形成第二绝缘膜，使得在所述存储单元栅电极之间产生气隙; 形成两个选择栅电极; 在所述选择栅电极上形成碳侧壁; 将两个选择栅电极之间的杂质离子以侧壁作为掩模; 并除去碳侧壁。

4. 发明申请

US20080087935A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080087935A1
公开(公告)日：2008-04-17
申请号：US11772446
申请日：2007-07-02
申请人： Koichi MATSUNO
发明人： Koichi MATSUNO
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11521
摘要： A semiconductor device includes an element isolation region formed in the surface of a semiconductor substrate, a plurality of memory cell transistors having respective gate electrodes formed in an element forming region and a selective gate transistor located at an end of a row of a predetermined number of the memory cell transistors. The element isolation insulating film formed at a part of the element isolation region adjacent to the selective gate transistor includes a first insulating film comprised of a coating oxide film buried in the trench so as to cover an inner part of the trench from a bottom of the trench to a predetermined depth and a second insulating film which is formed so as to cover the upper side of the first insulating film and the sidewall of the trench and has resistance to a wet etching process.
摘要翻译：半导体器件包括形成在半导体衬底的表面中的元件隔离区域，具有形成在元件形成区域中的各个栅电极的多个存储单元晶体管和位于行的预定数量的行的末端的选择栅极晶体管存储单元晶体管。形成在与选择栅极晶体管相邻的元件隔离区域的一部分的元件隔离绝缘膜包括第一绝缘膜，该第一绝缘膜由埋在沟槽中的涂覆氧化物膜构成，从而从该底部覆盖沟槽的内部沟槽到预定深度，第二绝缘膜形成为覆盖第一绝缘膜的上侧和沟槽的侧壁，并具有耐湿蚀刻工艺的能力。

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