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1. 发明授权

US5132573A Semiconductor gate array device compatible with ECL signals and/or TTL signals 失效
标题翻译：半导体门阵列器件兼容ECL信号和/或TTL信号
公开(公告)号：US5132573A
公开(公告)日：1992-07-21
申请号：US618691
申请日：1990-11-27
申请人： Yoshihiro Tsuru , Takashi Kuraishi , Fumiaki Matsuzaki , Takaharu Morishige
发明人： Yoshihiro Tsuru , Takashi Kuraishi , Fumiaki Matsuzaki , Takaharu Morishige
IPC分类号： H01L21/82 , H01L27/118 , H03K19/0175 , H03K19/018 , H03K19/173
CPC分类号： H01L27/11898
摘要： A semiconductor gate array device compatible with ECL and/or TTL, wherein the input buffer unit includes a TTL input stage, an ECL input stage and a common output stage, and the output buffer unit includes a common input stage, an ECL output stage and a TTL output stage. When the device is to be used as a TTL input interface, the TTL input stage and the common output stage are coupled together and when the device is to be used as an ECL input interface, the ECL input stage and the common output stage are coupled together. When used as a TTL output interface, the common input stage and the TTL output stage are coupled together and when used as an ECL output interface, the common input stage and the ECL output stage are coupled together. Therefore, the input/output interfaces exhibit general applicability to meet the user's demands, yet enabling the layout areas of the input and output buffer portions to be decreased.

2. 发明授权

US5666520A Graphics display system including graphics processor having a register storing a series of vertex data relating to a polygonal line 失效
标题翻译：图形显示系统，包括具有存储与多边形线相关的一系列顶点数据的寄存器的图形处理器
公开(公告)号：US5666520A
公开(公告)日：1997-09-09
申请号：US215244
申请日：1994-03-21
申请人： Ryo Fujita , Kazuhisa Takami , Mitsuru Soga , Koji Ozawa , Takaharu Morishige , Kazuyoshi Koga
发明人： Ryo Fujita , Kazuhisa Takami , Mitsuru Soga , Koji Ozawa , Takaharu Morishige , Kazuyoshi Koga
IPC分类号： G06T1/20 , G06T11/20 , G06F12/00
CPC分类号： G06T11/203 , G06T1/20
摘要： A graphics display system includes a host processor calculating graphic data and providing the graphic data to a graphics processor, and frame memories which store the graphic pixel data and supply display data to display devices. The graphics display system also includes a first register group which stores the graphics data, a second register group which converts and/or stores the data in the first register group, a pixel generator which generates pixels according to the graphic data in the second register group, and a plotter which writes the pixel data generated in the pixel generator in the frame memories. The second register group fetches the data from the first register group when the host processor issues a command for plotting, holds the data previously written by the host processor. At the same time, when the host processor issues a command for plotting, the specified graphic type is written in the graphic processor as sell as data calculated based on the first and second register groups.
摘要翻译：图形显示系统包括主处理器，其计算图形数据并将图形数据提供给图形处理器，以及存储图形像素数据并向显示装置提供显示数据的帧存储器。图形显示系统还包括存储图形数据的第一寄存器组，在第一寄存器组中转换和/或存储数据的第二寄存器组，根据第二寄存器组中的图形数据生成像素的像素生成器，以及将在像素生成器中生成的像素数据写入帧存储器的绘图仪。当主机处理器发出绘制命令时，第二个寄存器组从第一个寄存器组中获取数据，保存由主机处理器先前写入的数据。同时，当主机处理器发出用于绘图的命令时，指定的图形类型以作为基于第一和第二寄存器组计算的数据作为卖出而被写入图形处理器。

3. 发明授权

US5847715A Graphics display system including parallel graphics processors executing Bresenham's algorithm 失效
标题翻译：图形显示系统包括执行Bresenham算法的并行图形处理器
公开(公告)号：US5847715A
公开(公告)日：1998-12-08
申请号：US856081
申请日：1997-05-14
申请人： Ryo Fujita , Kazuhisa Takami , Mitsuru Soga , Koji Ozawa , Takaharu Morishige , Kazuyoshi Koga
发明人： Ryo Fujita , Kazuhisa Takami , Mitsuru Soga , Koji Ozawa , Takaharu Morishige , Kazuyoshi Koga
IPC分类号： G06T1/20 , G06T11/20 , G06F17/10
CPC分类号： G06T11/203 , G06T1/20
摘要： A graphics display system includes a host processor calculating graphic data and providing the graphic data to a graphics processor, and frame memories which store the graphic pixel data and supply display data to display devices. The graphics display system also includes a first register group which stores the graphics data, a second register group which converts and/or stores the data in the first register group, a pixel generator which generates pixels according to the graphic data in the second register group, and a plotter which writes the pixel data generated in the pixel generator in the frame memories. The second register group fetches the data from the first register group when the host processor issues a command for plotting, holds the data previously written by the host processor. At the same time, when the host processor issues a command for plotting, the specified graphic type is written in the graphic processor as well as data calculated based on the first and second register groups.
摘要翻译：图形显示系统包括主处理器，其计算图形数据并将图形数据提供给图形处理器，以及存储图形像素数据并向显示装置提供显示数据的帧存储器。图形显示系统还包括存储图形数据的第一寄存器组，在第一寄存器组中转换和/或存储数据的第二寄存器组，根据第二寄存器组中的图形数据生成像素的像素生成器，以及将在像素生成器中生成的像素数据写入帧存储器的绘图仪。当主机处理器发出绘制命令时，第二个寄存器组从第一个寄存器组中获取数据，保存由主机处理器先前写入的数据。同时，当主机处理器发出绘制命令时，指定的图形类型被写入图形处理器以及基于第一和第二寄存器组计算的数据。

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