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1. 发明申请

US20070091678A1 Memory system and operating method of same 有权
标题翻译：内存系统和操作方法相同
公开(公告)号：US20070091678A1
公开(公告)日：2007-04-26
申请号：US11583129
申请日：2006-10-19
申请人： Yoshiharu Kato , Yoshihiro Takemae , Toshio Ogawa , Tetsuhiko Endoh , Yoshinori Okajima
发明人： Yoshiharu Kato , Yoshihiro Takemae , Toshio Ogawa , Tetsuhiko Endoh , Yoshinori Okajima
IPC分类号： G11C16/06
CPC分类号： G11C16/32 , G06F11/1068 , G11C7/1006 , G11C2029/0411 , G11C2207/104
摘要： A volatile memory has a volatile additional area for storing an error correction code for a nonvolatile memory. Data stored in the nonvolatile memory are transferred to the volatile memory together with the error correction code without making an error correction. Thus, data transfer time from the nonvolatile memory to the volatile memory can be shortened. As a result, it is possible to shorten the time from beginning of the data transfer from the nonvolatile memory to the volatile memory to a point at which data becomes accessible.
摘要翻译：易失性存储器具有用于存储用于非易失性存储器的纠错码的易失性附加区域。存储在非易失性存储器中的数据与错误校正码一起传送到易失性存储器，而不进行纠错。因此，可以缩短从非易失性存储器到易失性存储器的数据传送时间。结果，可以缩短从非易失性存储器到易失性存储器的数据传输开始到数据可访问的时间。

2. 发明申请

US20070091989A1 Signal interface 有权
标题翻译：信号接口
公开(公告)号：US20070091989A1
公开(公告)日：2007-04-26
申请号：US11583130
申请日：2006-10-19
申请人： Yoshiharu Kato , Yoshihiro Takemae , Toshio Ogawa , Tetsuhiko Endoh , Yoshinori Okajima
发明人： Yoshiharu Kato , Yoshihiro Takemae , Toshio Ogawa , Tetsuhiko Endoh , Yoshinori Okajima
IPC分类号： H04L5/16 , H04L25/00
CPC分类号： H04L25/0282 , H04L5/04 , H04L25/0294
摘要： Plural transmitter units generate plural currents corresponding to plural logical values, respectively, and propagate the currents to a common signal line. The common signal line synthesizes the currents generated by the transmitter units, and propagates them to a receiver unit as a synthetic current. The receiver unit restores the logical values the transmitter units generated, in accordance with the synthetic current. The values of the currents the transmitter units generate in correspondence with the logical values each differ, so that the value of the synthetic current can be changed for every combination of logical values. Accordingly, the receiver unit can restore the logical values outputted from the respective transmitter units, based on the synthetic current. That is, employing the common signal line enables signals transmitted from the transmitter units to be simultaneously received. Consequently, the number of signal lines laid between the transmitter units and the receiver unit is reduced.
摘要翻译：多个发射机单元分别产生对应于多个逻辑值的多个电流，并将电流传播到公共信号线。公共信号线合成由发射机单元产生的电流，并将其作为合成电流传播到接收机单元。接收器单元根据合成电流恢复发射机单元产生的逻辑值。发射机单元对应于逻辑值产生的电流值各自不同，使得可以针对逻辑值的每个组合来改变合成电流的值。因此，接收机单元可以基于合成电流来恢复从各个发射机单元输出的逻辑值。也就是说，采用公共信号线使得能够同时接收从发送单元发送的信号。因此，放置在发射机单元和接收机单元之间的信号线的数量减少。

3. 发明授权

US07827468B2 Memory system including nonvolatile memory and volatile memory and operating method of same 有权
标题翻译：存储系统包括非易失性存储器和易失性存储器及其操作方法
公开(公告)号：US07827468B2
公开(公告)日：2010-11-02
申请号：US11583129
申请日：2006-10-19
申请人： Yoshiharu Kato , Yoshihiro Takemae , Toshio Ogawa , Tetsuhiko Endoh , Yoshinori Okajima
发明人： Yoshiharu Kato , Yoshihiro Takemae , Toshio Ogawa , Tetsuhiko Endoh , Yoshinori Okajima
IPC分类号： G11C29/00
CPC分类号： G11C16/32 , G06F11/1068 , G11C7/1006 , G11C2029/0411 , G11C2207/104
摘要： A volatile memory has a volatile additional area for storing an error correction code for a nonvolatile memory. Data stored in the nonvolatile memory are transferred to the volatile memory together with the error correction code without making an error correction. Thus, data transfer time from the nonvolatile memory to the volatile memory can be shortened. As a result, it is possible to shorten the time from beginning of the data transfer from the nonvolatile memory to the volatile memory to a point at which data becomes accessible.
摘要翻译：易失性存储器具有用于存储用于非易失性存储器的纠错码的易失性附加区域。存储在非易失性存储器中的数据与错误校正码一起传送到易失性存储器，而不进行纠错。因此，可以缩短从非易失性存储器到易失性存储器的数据传送时间。结果，可以缩短从非易失性存储器到易失性存储器的数据传输开始到数据可访问的时间。

4. 发明授权

US07388791B2 Signal interface 有权
标题翻译：信号接口
公开(公告)号：US07388791B2
公开(公告)日：2008-06-17
申请号：US11583130
申请日：2006-10-19
申请人： Yoshiharu Kato , Yoshihiro Takemae , Toshio Ogawa , Tetsuhiko Endoh , Yoshinori Okajima
发明人： Yoshiharu Kato , Yoshihiro Takemae , Toshio Ogawa , Tetsuhiko Endoh , Yoshinori Okajima
IPC分类号： G11C7/10
CPC分类号： H04L25/0282 , H04L5/04 , H04L25/0294
摘要： Plural transmitter units generate plural currents corresponding to plural logical values, respectively, and propagate the currents to a common signal line. The common signal line synthesizes the currents generated by the transmitter units, and propagates them to a receiver unit as a synthetic current. The receiver unit restores the logical values the transmitter units generated, in accordance with the synthetic current. The values of the currents the transmitter units generate in correspondence with the logical values each differ, so that the value of the synthetic current can be changed for every combination of logical values. Accordingly, the receiver unit can restore the logical values outputted from the respective transmitter units, based on the synthetic current. That is, employing the common signal line enables signals transmitted from the transmitter units to be simultaneously received. Consequently, the number of signal lines laid between the transmitter units and the receiver unit is reduced.
摘要翻译：多个发射机单元分别产生对应于多个逻辑值的多个电流，并将电流传播到公共信号线。公共信号线合成由发射机单元产生的电流，并将其作为合成电流传播到接收机单元。接收器单元根据合成电流恢复发射机单元产生的逻辑值。发射机单元对应于逻辑值产生的电流值各自不同，使得可以针对逻辑值的每个组合来改变合成电流的值。因此，接收机单元可以基于合成电流来恢复从各个发射机单元输出的逻辑值。也就是说，采用公共信号线使得能够同时接收从发送单元发送的信号。因此，放置在发射机单元和接收机单元之间的信号线的数量减少。

5. 发明授权

US07937645B2 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US07937645B2
公开(公告)日：2011-05-03
申请号：US11443109
申请日：2006-05-31
申请人： Toshio Ogawa , Yoshihiro Takemae , Yoshinori Okajima , Tetsuhiko Endo , Yasuro Matsuzaki
发明人： Toshio Ogawa , Yoshihiro Takemae , Yoshinori Okajima , Tetsuhiko Endo , Yasuro Matsuzaki
IPC分类号： G11C29/00
CPC分类号： G11C29/42
摘要： A conversion control unit sets a converting function of a write data conversion unit or a read data conversion unit enabled or disabled for each controller. Accordingly, for a controller which needs original external data, the external data can be inputted and outputted, whereas for a controller which needs converted internal data, the internal data can be inputted and outputted. A data converting function of a conventional controller can be realized in a semiconductor memory, which can reduce the load on the controller. As a result, the performance of a system can be improved. A disabled controller which has no access right cannot read correct data (original data before conversion). Hence, the security of data written into the semiconductor memory can be protected.
摘要翻译：转换控制单元设置对每个控制器启用或禁用的写数据转换单元或读数据转换单元的转换功能。因此，对于需要原始外部数据的控制器，可以输入和输出外部数据，而对于需要转换的内部数据的控制器，可以输入和输出内部数据。可以在半导体存储器中实现传统控制器的数据转换功能，这可以减少控制器上的负载。结果，可以提高系统的性能。无权访问的无效控制器无法读取正确的数据（转换前的原始数据）。因此，可以保护写入半导体存储器的数据的安全性。

6. 发明授权

US07941730B2 Memory system 有权
标题翻译：内存系统
公开(公告)号：US07941730B2
公开(公告)日：2011-05-10
申请号：US11443031
申请日：2006-05-31
申请人： Toshio Ogawa , Yoshihiro Takemae , Yoshinori Okajima , Tetsuhiko Endo , Yasuro Matsuzaki
发明人： Toshio Ogawa , Yoshihiro Takemae , Yoshinori Okajima , Tetsuhiko Endo , Yasuro Matsuzaki
IPC分类号： G06F11/10 , G06F13/14
CPC分类号： G11C7/10 , G06F11/1068 , G11C7/1045
摘要： A semiconductor memory has a field programmable unit in which logic to inter-convert external signals to be input/output to/from a memory system and internal signals to be input/output to/from a memory cell array is programmed. A program for constructing the logic of the field programmable unit is stored in a nonvolatile program memory unit. Through the field programmable unit, a controller can access the memory cell array, even when the interface of the controller accessing the semiconductor memory is different from an interface for accessing the memory cell array. Therefore, one kind of semiconductor memory can be used as plural kinds of semiconductor memories. This eliminates the need to develop plural kinds of semiconductor memories, reducing a development cost.
摘要翻译：半导体存储器具有现场可编程单元，其中将外部信号互相转换为存储器系统的输入/输出的逻辑和要从存储器单元阵列输入/输出的内部信号的逻辑被编程。用于构建现场可编程单元的逻辑的程序存储在非易失性程序存储单元中。通过现场可编程单元，即使当访问半导体存储器的控制器的接口与用于访问存储单元阵列的接口不同时，控制器也可以访问存储单元阵列。因此，可以使用一种半导体存储器作为多种半导体存储器。这消除了开发多种半导体存储器的需要，降低了开发成本。

7. 发明授权

US07417884B2 Memory system 有权
标题翻译：内存系统
公开(公告)号：US07417884B2
公开(公告)日：2008-08-26
申请号：US11443030
申请日：2006-05-31
申请人： Toshio Ogawa , Yoshihiro Takemae , Yoshinori Okajima , Tetsuhiko Endo , Yasuro Matsuzaki
发明人： Toshio Ogawa , Yoshihiro Takemae , Yoshinori Okajima , Tetsuhiko Endo , Yasuro Matsuzaki
IPC分类号： G11C5/06 , H04B10/00
CPC分类号： G06F13/4243 , G11C5/066 , G11C7/1006
摘要： A memory controller multiplexes access signals each consisting of a plurality of bits as optical signals and outputs the multiplexed optical signals. At this time, the optical signals whose wavelengths differ depending on memory devices are generated. A memory interface unit demultiplexes the multiplexed optical signals into the original optical signals and converts the demultiplexed optical signals into electrical signals. The memory interface unit determines to which of the memory devices the electrical signals resulting from the conversion should be outputted, according to the wavelengths of the demultiplexed optical signals. This frees the memory controller from a need for transmitting to the memory interface unit a signal for identifying the memory device. The memory interface unit need not include a decoding circuit for identifying the memory device.
摘要翻译：存储器控制器将每个由多个位组成的访问信号复用为光信号并输出复用的光信号。此时，产生根据存储器件波长不同的光信号。存储器接口单元将复用的光信号解复用为原始光信号，并将解复用的光信号转换为电信号。存储器接口单元根据解复用的光信号的波长来确定应该向哪个存储器件输出由转换产生的电信号。这使得存储器控制器不需要向存储器接口单元发送用于识别存储器件的信号。存储器接口单元不需要包括用于识别存储器件的解码电路。

8. 发明申请

US20070192527A1 Memory system 有权
标题翻译：内存系统
公开(公告)号：US20070192527A1
公开(公告)日：2007-08-16
申请号：US11443031
申请日：2006-05-31
申请人： Toshio Ogawa , Yoshihiro Takemae , Yoshinori Okajima , Tetsuhiko Endo , Yasuro Matsuzaki
发明人： Toshio Ogawa , Yoshihiro Takemae , Yoshinori Okajima , Tetsuhiko Endo , Yasuro Matsuzaki
IPC分类号： G06F12/00
CPC分类号： G11C7/10 , G06F11/1068 , G11C7/1045
摘要： A semiconductor memory has a field programmable unit in which logic to inter-convert external signals to be input/output to/from a memory system and internal signals to be input/output to/from a memory cell array is programmed. A program for constructing the logic of the field programmable unit is stored in a nonvolatile program memory unit. Through the field programmable unit, a controller can access the memory cell array, even when the interface of the controller accessing the semiconductor memory is different from an interface for accessing the memory cell array. Therefore, one kind of semiconductor memory can be used as plural kinds of semiconductor memories. This eliminates the need to develop plural kinds of semiconductor memories, reducing a development cost.
摘要翻译：半导体存储器具有现场可编程单元，其中将外部信号互相转换为存储器系统的输入/输出的逻辑和要从存储器单元阵列输入/输出的内部信号的逻辑被编程。用于构建现场可编程单元的逻辑的程序存储在非易失性程序存储单元中。通过现场可编程单元，即使当访问半导体存储器的控制器的接口与用于访问存储单元阵列的接口不同时，控制器也可以访问存储单元阵列。因此，可以使用一种半导体存储器作为多种半导体存储器。这消除了开发多种半导体存储器的需要，降低了开发成本。

9. 发明授权

US07561455B2 Memory system using single wavelength optical transmission 有权
标题翻译：内存系统采用单波长光传输
公开(公告)号：US07561455B2
公开(公告)日：2009-07-14
申请号：US11498175
申请日：2006-08-03
申请人： Toshio Ogawa , Yoshihiro Takemae , Yoshinori Okajima , Tetsuhiko Endo , Yasuro Matsuzaki
发明人： Toshio Ogawa , Yoshihiro Takemae , Yoshinori Okajima , Tetsuhiko Endo , Yasuro Matsuzaki
IPC分类号： G11C13/04
CPC分类号： G06F13/4072
摘要： A controller converts a parallel command signal and address signal, or a parallel write data signal into a first serial signal, and outputs the converted signal as a first optical signal with a single wavelength to a memory device via an optical transmission line. The memory device converts the first optical signal into the original parallel command signal, address signal, and write data signal, and outputs the converted parallel signals to a memory unit. The memory device converts a parallel read data signal from the memory unit into a second serial signal, and outputs the converted signal to the controller via the optical transmission line as a second optical signal with a single wavelength. It is unnecessary to transmit the optical signal using an optical multiplexer, an optical demultiplexer, etc., thereby improving transmission rate of signals transmitted between the controller and the memory device at minimum cost.
摘要翻译：控制器将并行命令信号和地址信号或并行写入数据信号转换为第一串行信号，并将转换的信号作为具有单一波长的第一光信号通过光传输线输出到存储器件。存储器件将第一光信号转换为原始并行命令信号，地址信号和写数据信号，并将转换的并行信号输出到存储器单元。存储器装置将来自存储器单元的并行读取数据信号转换为第二串行信号，并且经由光传输线路将转换的信号作为具有单个波长的第二光信号输出到控制器。不需要使用光复用器，光解复用器等来发送光信号，从而以最小的成本提高在控制器和存储器件之间传输的信号的传输速率。

10. 发明申请

US20070230231A1 Memory system 有权
标题翻译：内存系统
公开(公告)号：US20070230231A1
公开(公告)日：2007-10-04
申请号：US11498175
申请日：2006-08-03
申请人： Toshio Ogawa , Yoshihiro Takemae , Yoshinori Okajima , Tetsuhiko Endo , Yasuro Matsuzaki
发明人： Toshio Ogawa , Yoshihiro Takemae , Yoshinori Okajima , Tetsuhiko Endo , Yasuro Matsuzaki
IPC分类号： G11C13/04
CPC分类号： G06F13/4072
摘要： A controller converts a parallel command signal and address signal, or a parallel write data signal into a first serial signal, and outputs the converted signal as a first optical signal with a single wavelength to a memory device via an optical transmission line. The memory device converts the first optical signal into the original parallel command signal, address signal, and write data signal, and outputs the converted parallel signals to a memory unit. The memory device converts a parallel read data signal from the memory unit into a second serial signal, and outputs the converted signal to the controller via the optical transmission line as a second optical signal with a single wavelength. It is unnecessary to transmit the optical signal using an optical multiplexer, an optical demultiplexer, etc., thereby improving transmission rate of signals transmitted between the controller and the memory device at minimum cost.
摘要翻译：控制器将并行命令信号和地址信号或并行写入数据信号转换为第一串行信号，并将转换的信号作为具有单一波长的第一光信号通过光传输线输出到存储器件。存储器件将第一光信号转换为原始并行命令信号，地址信号和写数据信号，并将转换的并行信号输出到存储器单元。存储器装置将来自存储器单元的并行读取数据信号转换为第二串行信号，并且经由光传输线路将转换的信号作为具有单个波长的第二光信号输出到控制器。不需要使用光复用器，光解复用器等来发送光信号，从而以最小的成本提高在控制器和存储器件之间传输的信号的传输速率。

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