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1. 发明授权

US06501691B2 Word-line deficiency detection method for semiconductor memory device 有权
标题翻译：半导体存储器件的字线缺陷检测方法
公开(公告)号：US06501691B2
公开(公告)日：2002-12-31
申请号：US09768459
申请日：2001-01-25
申请人： Satoru Kawamoto , Motoki Mizutani , Shinji Nagai , Yoshiharu Kato
发明人： Satoru Kawamoto , Motoki Mizutani , Shinji Nagai , Yoshiharu Kato
IPC分类号： G11C700
CPC分类号： G11C29/025 , G11C17/14 , G11C29/02 , G11C29/50 , G11C2029/0403
摘要： A semiconductor memory device having a burn-in test capability. The semiconductor memory device includes a detection circuit, which is connected to the plurality of word lines. The detection circuit detects whether a stress voltage for a burn-in test has been applied to all of the word lines along their entire lengths in the burn-in test.
摘要翻译：具有老化测试能力的半导体存储器件。半导体存储器件包括连接到多个字线的检测电路。检测电路检测在老化测试中，老化测试的应力电压是否已沿其整个长度应用于所有字线。

2. 发明授权

US06418072B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US06418072B2
公开(公告)日：2002-07-09
申请号：US09750352
申请日：2000-12-29
申请人： Yoshichika Nakaya , Shinichiro Ikeda , Yoshiharu Kato , Satoru Kawamoto
发明人： Yoshichika Nakaya , Shinichiro Ikeda , Yoshiharu Kato , Satoru Kawamoto
IPC分类号： G11C700
CPC分类号： G11C29/40
摘要： The first switching circuit selects data of a predetermined bit from the input/output data in accordance with each of a plurality of testing modes and outputs the selected data as testing data. The second switching circuits receive the testing data and each bit of the input/output data, and select one of the input/output data and the testing data in accordance with the operation mode. In detail, each bit of the input/output data is respectively outputted to the memory cells during normal operation mode, and during testing mode the testing data is selected to be outputted to the memory cells as the common input/output data. Thus, write control for multiple kinds of data compressing test can be performed by using the simple first and second switching circuits. As a result, the control circuit for the data compressing test can be reduced in layout size.
摘要翻译：第一开关电路根据多个测试模式中的每一个从输入/输出数据中选择预定位的数据，并输出所选择的数据作为测试数据。第二开关电路接收测试数据和输入/输出数据的每一位，并根据操作模式选择输入/输出数据和测试数据之一。详细地说，输入/输出数据的每一位在正常操作模式下分别输出到存储单元，在测试模式期间，选择测试数据作为公共输入/输出数据输出到存储单元。因此，可以通过使用简单的第一和第二开关电路来执行用于多种数据压缩测试的写入控制。结果，可以减少用于数据压缩测试的控制电路的布局尺寸。

3. 发明申请

US20070237014A1 Semiconductor memory device and method of controlling the semiconductor memory device 失效
标题翻译：半导体存储器件和控制半导体存储器件的方法
公开(公告)号：US20070237014A1
公开(公告)日：2007-10-11
申请号：US11806721
申请日：2007-06-04
申请人： Kazufumi Komura , Yoshiharu Kato , Satoru Kawamoto
发明人： Kazufumi Komura , Yoshiharu Kato , Satoru Kawamoto
IPC分类号： G11C7/00
CPC分类号： G11C11/4094 , G11C11/4076 , G11C2207/005
摘要： It is an object to provide a semiconductor memory device that can conduct the equalizing operation of bit lines with a low current consumption while maintaining a normal accessing speed and the chip area, and a control method thereof. In a semiconductor memory device of the shared sense amplification system, in a predetermined number of times which is (k−1) times or less among k-times of continuous word line selections of a selected memory block, the bit line separation gate of the unselected memory block is rendered conductive in the active period of the equalizing unit after the word line selection. Also, a circuit that equalizes a wiring higher in the capacity component is driven by a higher voltage level according to the wiring capacity component of the sense amplification power supply line and the bit lines, to thereby equalize the power supply line and the bit line in the equal time, thereby being capable of preventing the short-circuiting within the sense amplifier.
摘要翻译：本发明的目的是提供一种半导体存储器件及其控制方法，该半导体存储器件可以在保持正常访问速度和芯片面积的同时以低电流消耗进行位线的均衡操作。在共享读出放大系统的半导体存储器件中，在所选择的存储器块的连续字线选择的k次之间的预定次数（k-1）倍以下的情况下，位线分离门未选择的存储块在字线选择之后的均衡单元的有效周期内变为导通。此外，根据感测放大电源线和位线的布线电容分量，通过较高的电压电平驱动均衡电容分量较高的布线的电路，从而使电源线和位线的均匀化相等的时间，从而能够防止读出放大器内的短路。

4. 发明授权

US06972487B2 Multi chip package structure having a plurality of semiconductor chips mounted in the same package 有权
标题翻译：具有安装在相同封装中的多个半导体芯片的多芯片封装结构
公开(公告)号：US06972487B2
公开(公告)日：2005-12-06
申请号：US10058877
申请日：2002-01-25
申请人： Yoshiharu Kato , Satoru Kawamoto , Fumihiko Taniguchi , Tetsuya Hiraoka , Akira Takashima
发明人： Yoshiharu Kato , Satoru Kawamoto , Fumihiko Taniguchi , Tetsuya Hiraoka , Akira Takashima
IPC分类号： H01L21/66 , H01L23/48 , H01L25/065 , H01L25/18 , H01L23/52
CPC分类号： H01L22/22 , H01L23/544 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L2223/5442 , H01L2223/54426 , H01L2223/5448 , H01L2224/05554 , H01L2224/32145 , H01L2224/48091 , H01L2224/48135 , H01L2224/48137 , H01L2224/48145 , H01L2224/48227 , H01L2224/4826 , H01L2224/48465 , H01L2224/49175 , H01L2224/4943 , H01L2224/73265 , H01L2224/8513 , H01L2225/06506 , H01L2225/0651 , H01L2225/06555 , H01L2225/06562 , H01L2225/06586 , H01L2225/06593 , H01L2225/06596 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01039 , H01L2924/014 , H01L2924/10161 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599
摘要： The present invention relates to a semiconductor device having an MCP (Multi Chip Package) structure in which a plurality of semiconductor chips are mounted in the same package, a manufacturing method therefor and a semiconductor Substrate used therein. Atop a first semiconductor chip that is a memory chip is mounted a second Semiconductor chip that is a logic chip, with a first functional chip and a second functional chip that together form the first semiconductor chip being joined together via an unsliced scribe line. Additionally, a first functional chip and a second functional chip are given the same chip composition (32-bit memory) and respectively rotated 180 degrees relative to each other. These configurations are intended to improve performance, reduce costs and improve yield.
摘要翻译：本发明涉及具有MCP（多芯片封装）结构的半导体器件，其中多个半导体芯片安装在相同的封装中，其制造方法和其中使用的半导体衬底。在作为存储芯片的第一半导体芯片的顶部安装有作为逻辑芯片的第二半导体芯片，具有第一功能芯片和第二功能芯片，第一功能芯片和第二功能芯片一起形成通过未经切割的划线连接在一起的第一半导体芯片。此外，第一功能芯片和第二功能芯片被赋予相同的芯片组合（32位存储器）并且分别相对于彼此旋转180度。这些配置旨在提高性能，降低成本并提高产量。

5. 发明申请

US20050161794A1 Semiconductor device, method for manufacturing the semiconductor device and semiconductor substrate 审中-公开
标题翻译：半导体器件，半导体器件和半导体衬底的制造方法
公开(公告)号：US20050161794A1
公开(公告)日：2005-07-28
申请号：US11080414
申请日：2005-03-16
申请人： Yoshiharu Kato , Satoru Kawamoto , Fumihiko Taniguchi , Tetsuya Hiraoka , Akira Takashima
发明人： Yoshiharu Kato , Satoru Kawamoto , Fumihiko Taniguchi , Tetsuya Hiraoka , Akira Takashima
IPC分类号： H01L21/66 , H01L23/48 , H01L25/065 , H01L25/18
CPC分类号： H01L22/22 , H01L23/544 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L2223/5442 , H01L2223/54426 , H01L2223/5448 , H01L2224/05554 , H01L2224/32145 , H01L2224/48091 , H01L2224/48135 , H01L2224/48137 , H01L2224/48145 , H01L2224/48227 , H01L2224/4826 , H01L2224/48465 , H01L2224/49175 , H01L2224/4943 , H01L2224/73265 , H01L2224/8513 , H01L2225/06506 , H01L2225/0651 , H01L2225/06555 , H01L2225/06562 , H01L2225/06586 , H01L2225/06593 , H01L2225/06596 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01039 , H01L2924/014 , H01L2924/10161 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599
摘要： The present invention relates to a semiconductor device having an MCP (Multi Chip Package) structure in which a plurality of semiconductor chips are mounted in the same package, a manufacturing method therefor and a semiconductor substrate used therein. Atop a first semiconductor chip that is a memory chip is mounted a second semiconductor chip that is a logic chip, with a first functional chip and a second functional chip that together form the first semiconductor chip being joined together via an unsliced scribe line. Additionally, a first functional chip and a second functional chip are given the same chip composition (32-bit memory) and respectively rotated 180 degrees relative to each other. These configurations are intended to improve performance, reduce costs and improve yield.
摘要翻译：本发明涉及具有MCP（多芯片封装）结构的半导体器件，其中多个半导体芯片安装在相同的封装中，其制造方法和其中使用的半导体衬底。在作为存储器芯片的第一半导体芯片的顶部安装作为逻辑芯片的第二半导体芯片，其中第一功能芯片和第二功能芯片一起形成通过未切割的划线连接在一起的第一半导体芯片。此外，第一功能芯片和第二功能芯片被赋予相同的芯片组合（32位存储器）并且分别相对于彼此旋转180度。这些配置旨在提高性能，降低成本并提高产量。

6. 发明申请

US20050157574A1 Semiconductor memory device and method of controlling the semiconductor memory device 有权
标题翻译：半导体存储器件和控制半导体存储器件的方法
公开(公告)号：US20050157574A1
公开(公告)日：2005-07-21
申请号：US11058302
申请日：2005-02-16
申请人： Kazufumi Komura , Yoshiharu Kato , Satoru Kawamoto
发明人： Kazufumi Komura , Yoshiharu Kato , Satoru Kawamoto
IPC分类号： G11C7/00 , G11C11/4076 , G11C11/4094
CPC分类号： G11C11/4094 , G11C11/4076 , G11C2207/005
摘要： It is an object to provide a semiconductor memory device that can conduct the equalizing operation of bit lines with a low current consumption while maintaining a normal accessing speed and the chip area, and a control method thereof. In a semiconductor memory device of the shared sense amplification system, in a predetermined number of times which is (k−1) times or less among k-times of continuous word line selections of a selected memory block, the bit line separation gate of the unselected memory block is rendered conductive in the active period of the equalizing unit after the word line selection. Also, a circuit that equalizes a wiring higher in the capacity component is driven by a higher voltage level according to the wiring capacity component of the sense amplification power supply line and the bit lines, to thereby equalize the power supply line and the bit line in the equal time, thereby being capable of preventing the short-circuiting within the sense amplifier.
摘要翻译：本发明的目的是提供一种半导体存储器件及其控制方法，该半导体存储器件可以在保持正常访问速度和芯片面积的同时以低电流消耗进行位线的均衡操作。在共享读出放大系统的半导体存储器件中，在所选择的存储器块的连续字线选择的k次之间的预定次数（k-1）倍以下的情况下，位线分离门未选择的存储块在字线选择之后的均衡单元的有效周期内变为导通。此外，根据感测放大电源线和位线的布线电容分量，通过较高的电压电平驱动均衡电容分量较高的布线的电路，从而使电源线和位线的均匀化相等的时间，从而能够防止读出放大器内的短路。

7. 发明授权

US06847540B2 Semiconductor memory device and control method thereof 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US06847540B2
公开(公告)日：2005-01-25
申请号：US10404153
申请日：2003-04-02
申请人： Yoshiharu Kato , Satoru Kawamoto
发明人： Yoshiharu Kato , Satoru Kawamoto
IPC分类号： G11C11/404 , G11C7/14 , G11C7/22 , G11C11/34 , G11C11/407 , G11C11/4074 , G11C11/4076 , G11C11/4099 , H01L21/8242 , H01L27/108 , G11C11/24
CPC分类号： G11C7/227 , G11C7/14 , G11C7/22 , G11C11/4074 , G11C11/4076 , G11C11/4099
摘要： A semiconductor memory device, in which a cell plate potential does not fluctuate even when the device state is changed from a state without stored charge in all charge storage nodes of the cell capacitors at power-on to an access operation state, comprises NMOS transistors M1 to Mk for connecting a line VPR as a feeder for a reference voltage VPR from a reference voltage generation circuit with a line VCP as a feeder for a reference voltage VCP from the reference voltage generation circuit in each of cell blocks B1 to Bk. Gate terminals of the NMOS transistors M1 to Mk are connected to a common signal φCPR. The signal φCPR outputs a positive logical level at a predetermined time after power-on. By providing the NMOS transistors M1 to Mk for short-circuiting the line VPR with the line VCP in each of the cell blocks B1 to Bk, both lines are short-circuited in each of the cell blocks B1 to Bk.
摘要翻译：即使当器件状态从电源电容器的所有电荷存储节点中的没有存储电荷的状态改变到接通操作状态时，单元板电位也不波动的半导体存储器件包括NMOS晶体管M1 到Mk，用于将来自参考电压生成电路的参考电压VPR的线路VPR作为用于参考电压VCP的馈线（用于参考电压VCP的馈线）的每个单元块B1至Bk中的参考电压产生电路连接。 NMOS晶体管M1至Mk的栅极端子连接到公共信号phiCPR。信号phiCPR在上电之后的预定时间输出正逻辑电平。通过在每个单元块B1至Bk中设置用于使线VPR与线VCP短路的NMOS晶体管M1至Mk，在每个单元块B1至Bk中两条线都短路。

8. 发明授权

US06839293B2 Word-line deficiency detection method for semiconductor memory device 失效
标题翻译：半导体存储器件的字线缺陷检测方法
公开(公告)号：US06839293B2
公开(公告)日：2005-01-04
申请号：US10288461
申请日：2002-11-06
申请人： Satoru Kawamoto , Motoki Mizutani , Shinji Nagai , Yoshiharu Kato
发明人： Satoru Kawamoto , Motoki Mizutani , Shinji Nagai , Yoshiharu Kato
IPC分类号： G01R31/26 , G01R31/28 , G11C11/401 , G11C29/02 , G11C29/04 , G11C29/06 , G11C29/50 , G11C29/00 , G11C7/00
CPC分类号： G11C29/025 , G11C17/14 , G11C29/02 , G11C29/50 , G11C2029/0403
摘要： A semiconductor memory device having a burn-in test capability. The semiconductor memory device includes a detection circuit, which is connected to the plurality of word lines. The detection circuit detects whether a stress voltage for a burn-in test has been applied to all of the word lines along their entire lengths in the burn-in test.
摘要翻译：具有老化测试能力的半导体存储器件。半导体存储器件包括连接到多个字线的检测电路。检测电路检测在老化测试中，老化测试的应力电压是否已沿其整个长度应用于所有字线。

9. 发明授权

US06567298B2 Semiconductor memory device and control method thereof 有权
公开(公告)号：US06567298B2
公开(公告)日：2003-05-20
申请号：US09983148
申请日：2001-10-23
申请人： Yoshiharu Kato , Satoru Kawamoto
发明人： Yoshiharu Kato , Satoru Kawamoto
IPC分类号： G11C1124
CPC分类号： G11C7/227 , G11C7/14 , G11C7/22 , G11C11/4074 , G11C11/4076 , G11C11/4099
摘要： A semiconductor memory device, in which a cell plate potential does not fluctuate even when the device state is changed from a state without stored charge in all charge storage nodes of the cell capacitors at power-on to an access operation state, comprises NMOS transistors M1 to Mk for connecting a line VPR as a feeder for a reference voltage VPR from a reference voltage generation circuit with a line VCP as a feeder for a reference voltage VCP from the reference voltage generation circuit in each of cell blocks B1 to Bk. Gate terminals of the NMOS transistors M1 to Mk are connected to a common signal &phgr;CPR. The signal &phgr;CPR outputs a positive logical level at a predetermined time after power-on. By providing the NMOS transistors M1 to Mk for short-circuiting the line VPR with the line VCP in each of the cell blocks B1 to Bk, both lines are short-circuited in each of the cell blocks B1 to Bk.

10. 发明授权

US06297999B2 Semiconductor memory device and method for setting stress voltage 失效
标题翻译：半导体存储器件及设定应力电压的方法
公开(公告)号：US06297999B2
公开(公告)日：2001-10-02
申请号：US09784181
申请日：2001-02-16
申请人： Yoshiharu Kato , Satoru Kawamoto
发明人： Yoshiharu Kato , Satoru Kawamoto
IPC分类号： G11C2900
CPC分类号： G11C29/50 , G11C11/401
摘要： The present invention provides a semiconductor memory device that performs a burn-in test. The device includes word lines, pairs of bit lines, memory cells, sense amplifiers connected to the pairs of bit lines for amplifying a potential difference between the associated pair of bit lines, and a burn-in test control circuit for providing a stress voltage to the plurality of word lines and the pairs of bit lines to perform a burn-in test based on the burn-in control signal The burn-in test control circuit includes a potential difference setting circuit for selecting one of the first word lines so to generate a potential difference between at least one of the pairs of bit lines. The sense amplifiers amplify the potential difference to provide the stress voltage between the word lines and the associated pair of bit lines and between the bit lines of that pair.
摘要翻译：本发明提供一种执行老化测试的半导体存储器件。该器件包括字线，位线对，存储器单元，连接到位线对的读出放大器，用于放大相关联的位线对之间的电位差，以及用于提供应力电压的老化测试控制电路多个字线和位线对，以基于老化控制信号进行老化测试。老化测试控制电路包括：电位差设定电路，用于选择一个第一字线以产生至少一对位线之间的电位差。读出放大器放大电位差，以在字线和相关的位线对之间以及该对的位线之间提供应力电压。

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