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    • 2. 发明申请
    • Method of forming dual polysilicon gate of semiconductor device
    • 形成半导体器件的双重多晶硅栅极的方法
    • US20060189085A1
    • 2006-08-24
    • US11356998
    • 2006-02-17
    • Wook-je KimYong-chul Oh
    • Wook-je KimYong-chul Oh
    • H01L21/336
    • H01L21/823835H01L21/28061H01L21/823842
    • In a method of forming a dual polysilicon gate of a semiconductor device, a polysilicon layer is formed on a substrate divided into an NMOS region and a PMOS region. Then, a p-type impurity is implanted in the PMOS region. A thermal annealing process is performed that causes generation of a compound material at a top surface of the polysilicon layer in the PMOS region as a result of bonding between the p-type impurity and the polysilicon layer. A cleaning process is then performed. During the cleaning process, the compound material decreases an etch rate in the PMOS region, so that a height of the polysilicon layer in the NMOS region is reduced relative to that of the polysilicon layer in the PMOS region. Accordingly, an intended range of a threshold voltage can be obtained by blocking the p-type impurity in the PMOS region from penetrating into a gate insulation layer. Also, by maintaining an increased height of a gate transmission material in the cell region, a resistance increase is thereby prevented.
    • 在形成半导体器件的双重多晶硅栅极的方法中,在分成NMOS区域和PMOS区域的衬底上形成多晶硅层。 然后,在PMOS区域中注入p型杂质。 由于p型杂质和多晶硅层之间的结合,进行了在PMOS区域中的多晶硅层的顶面产生复合材料的热退火处理。 然后执行清洁处理。 在清洁过程中,复合材料降低了PMOS区域中的蚀刻速率,使得NMOS区域中的多晶硅层的高度相对于PMOS区域中的多晶硅层的高度减小。 因此,可以通过阻塞PMOS区中的p型杂质渗透到栅极绝缘层中来获得阈值电压的期望范围。 此外,通过保持电池区域中的栅极传输材料的高度增加,由此防止了电阻增加。
    • 7. 发明授权
    • Method of manufacturing semiconductor device
    • 制造半导体器件的方法
    • US08361860B2
    • 2013-01-29
    • US12656130
    • 2010-01-19
    • Jin-bum KimWook-je KimKwan-heum LeeYu-gyun ShinSun-ghil Lee
    • Jin-bum KimWook-je KimKwan-heum LeeYu-gyun ShinSun-ghil Lee
    • H01L21/8242
    • H01L21/7687H01L27/10855H01L28/91
    • A method of manufacturing a semiconductor device may include forming a first interlayer insulation layer on a substrate including at least one gate structure formed thereon, the substrate having a plurality of source/drain regions formed on both sides of the at least one gate structure, forming at least one buried contact plug on at least one of the plurality of source/drain regions and in the first interlayer insulation layer, forming a second interlayer insulation layer on the first interlayer insulation layer and the at least one buried contact plug, exposing the at least one buried contact plug in the second interlayer insulation layer by forming at least one contact hole, implanting ions in the at least one contact hole in order to create an amorphous upper portion of the at least one buried contact plug, depositing a lower electrode layer on the second interlayer insulation layer and the at least one contact hole, and forming a metal silicide layer in the amorphous upper portion of the at least one buried contact plug.
    • 制造半导体器件的方法可以包括在包括形成在其上的至少一个栅极结构的衬底上形成第一层间绝缘层,所述衬底具有形成在所述至少一个栅极结构的两侧上的多个源/漏区,形成 在所述多个源极/漏极区域和所述第一层间绝缘层中的至少一个上的至少一个埋置的接触插塞,在所述第一层间绝缘层和所述至少一个埋置的接触插塞上形成第二层间绝缘层, 通过形成至少一个接触孔,在所述至少一个接触孔中注入离子,以形成所述至少一个埋入接触插塞的非晶体上部,沉积下部电极层 在所述第二层间绝缘层和所述至少一个接触孔上,并且在所述非晶体上部形成金属硅化物层 的所述至少一个埋入式接触插塞。
    • 8. 发明申请
    • Method of manufacturing semiconductor device
    • 制造半导体器件的方法
    • US20100330758A1
    • 2010-12-30
    • US12656130
    • 2010-01-19
    • Jin-bum KimWook-je KimKwan-heum LeeYu-gyun ShinSun-ghil Lee
    • Jin-bum KimWook-je KimKwan-heum LeeYu-gyun ShinSun-ghil Lee
    • H01L21/8242H01L21/283
    • H01L21/7687H01L27/10855H01L28/91
    • A method of manufacturing a semiconductor device may include forming a first interlayer insulation layer on a substrate including at least one gate structure formed thereon, the substrate having a plurality of source/drain regions formed on both sides of the at least one gate structure, forming at least one buried contact plug on at least one of the plurality of source/drain regions and in the first interlayer insulation layer, forming a second interlayer insulation layer on the first interlayer insulation layer and the at least one buried contact plug, exposing the at least one buried contact plug in the second interlayer insulation layer by forming at least one contact hole, implanting ions in the at least one contact hole in order to create an amorphous upper portion of the at least one buried contact plug, depositing a lower electrode layer on the second interlayer insulation layer and the at least one contact hole, and forming a metal silicide layer in the amorphous upper portion of the at least one buried contact plug.
    • 制造半导体器件的方法可以包括在包括形成在其上的至少一个栅极结构的衬底上形成第一层间绝缘层,所述衬底具有形成在所述至少一个栅极结构的两侧上的多个源/漏区,形成 在所述多个源极/漏极区域和所述第一层间绝缘层中的至少一个上的至少一个埋置的接触插塞,在所述第一层间绝缘层和所述至少一个埋置的接触插塞上形成第二层间绝缘层, 通过形成至少一个接触孔,在所述至少一个接触孔中注入离子,以形成所述至少一个埋入接触插塞的非晶体上部,沉积下部电极层 在所述第二层间绝缘层和所述至少一个接触孔上,并且在所述非晶体上部形成金属硅化物层 的所述至少一个埋入式接触插塞。
    • 10. 发明授权
    • Semiconductor memory device with high operating current and method of manufacturing the same
    • 具有高工作电流的半导体存储器件及其制造方法
    • US07303955B2
    • 2007-12-04
    • US11300233
    • 2005-12-14
    • Wook-je Kim
    • Wook-je Kim
    • H01L21/336
    • H01L29/7843H01L21/76801H01L21/76831H01L21/76832H01L21/76897H01L21/823871H01L27/105H01L27/1052H01L27/11526H01L27/11546H01L29/6656
    • In a semiconductor memory device with a high operating current and a method of manufacturing the same, a semiconductor substrate is formed in which a memory cell region and a peripheral circuit region including an N-channel metal oxide semiconductor (NMOS) region and a P-channel metal oxide semiconductor (PMOS) region are defined. A gate electrode with sidewall spacers is formed in each of the memory cell region and the peripheral circuit region. Source and drain regions are formed in the semiconductor substrate at sides of the gate electrode to form metal oxide semiconductor (MOS) transistors. A first etch stop layer is formed on the semiconductor substrate where the MOS transistors are formed. A second etch stop layer is selectively formed in the NMOS region of the peripheral circuit region.
    • 在具有高工作电流的半导体存储器件及其制造方法中,形成半导体衬底,其中存储单元区域和包括N沟道金属氧化物半导体(NMOS)区域和P-沟道金属氧化物半导体区域的外围电路区域, 沟道金属氧化物半导体(PMOS)区域。 在每个存储单元区域和外围电路区域中形成具有侧壁间隔物的栅电极。 源极和漏极区域形成在栅极侧的半导体衬底中,以形成金属氧化物半导体(MOS)晶体管。 在形成MOS晶体管的半导体衬底上形成第一蚀刻停止层。 在外围电路区域的NMOS区域中选择性地形成第二蚀刻停止层。