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1. 发明申请

US20080252341A1 CLOCK SIGNAL DISTRIBUTION CIRCUIT AND INTERFACE APPARATUS USING THE SAME 审中-公开
标题翻译：使用相同的时钟信号分配电路和接口装置
公开(公告)号：US20080252341A1
公开(公告)日：2008-10-16
申请号：US11962969
申请日：2007-12-21
申请人： Yong-Ju Kim , Kun-Woo Park , Jong-Woon Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang
发明人： Yong-Ju Kim , Kun-Woo Park , Jong-Woon Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , G06F1/04 , H04L7/0008 , H04L7/033
摘要： A clock signal distribution circuit comprises a voltage control and distribution circuit configured to change a delay of a received clock signal in response to a control voltage and to generate a distributed clock signal, and control voltage generation circuit configured to generate the control voltage using a phase difference between received data and the distributed clock signal.
摘要翻译：时钟信号分配电路包括电压控制和分配电路，其被配置为响应于控制电压改变所接收的时钟信号的延迟并产生分布式时钟信号;以及控制电压生成电路，被配置为使用相位产生控制电压接收数据与分布式时钟信号之间的差异。

2. 发明授权

US07642824B2 PLL circuit and method of controlling the same 失效
标题翻译： PLL电路及其控制方法
公开(公告)号：US07642824B2
公开(公告)日：2010-01-05
申请号：US11819603
申请日：2007-06-28
申请人： Yong-Ju Kim , Kun-Woo Park , Jong-Woon Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang
发明人： Yong-Ju Kim , Kun-Woo Park , Jong-Woon Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang
IPC分类号： H03L7/093 , H03L7/08
CPC分类号： H03L7/0893 , H03L7/093 , H03L7/10
摘要： A PLL circuit includes a phase detector that compares the phase of an input clock with the phase of a feedback clock so as to generate pull-up and pull-down control signals. A low pass filter pumps a voltage in response to the pull-up and pull-down control signals, and removes a noise component from the pumped voltage so as to output a control voltage. A buffer that controls voltage so as to generate a bias voltage having a smaller swing width than the control voltage. A voltage controlled oscillator receives the bias voltage and oscillates an output clock. A clock divider divides the frequency of the output clock at a predetermined ratio so as to generate the feedback clock.
摘要翻译： PLL电路包括相位检测器，其将输入时钟的相位与反馈时钟的相位进行比较，以产生上拉和下拉控制信号。低通滤波器响应于上拉和下拉控制信号泵送电压，并从泵浦电压中去除噪声分量，以输出控制电压。控制电压以产生具有比控制电压更小的摆动宽度的偏置电压的缓冲器。压控振荡器接收偏置电压并振荡输出时钟。时钟分频器以预定的比例对输出时钟的频率进行分频，以产生反馈时钟。

3. 发明授权

US07741888B2 PLL circuit having loop filter and method of driving the same 有权
标题翻译：具有环路滤波器的PLL电路及其驱动方法
公开(公告)号：US07741888B2
公开(公告)日：2010-06-22
申请号：US11822103
申请日：2007-07-02
申请人： Yong-Ju Kim , Kun-Woo Park , Jong-Woon Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang
发明人： Yong-Ju Kim , Kun-Woo Park , Jong-Woon Kim , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang
IPC分类号： H03L7/06
CPC分类号： H03L7/093 , H03L7/10
摘要： A PLL circuit includes a phase detector that compares the phase of an input clock and the phase of a feedback clock and generates a pull-up control signal and a pull-down control signal. A loop filter pumps a voltage in response to the pull-up and pull-down control signals, filters the pumped voltage, and outputs a control voltage. A voltage controlled oscillator receives the control signal and oscillates an output clock. A clock divider divides the frequency of the output clock at a predetermined rate to generate the feedback clock. In the PLL circuit, the loop filter includes a compensator that compensates for a variation.
摘要翻译： PLL电路包括相位检测器，其将输入时钟的相位与反馈时钟的相位进行比较，并产生上拉控制信号和下拉控制信号。环路滤波器根据上拉和下拉控制信号抽取电压，对泵浦电压进行滤波，并输出一个控制电压。压控振荡器接收控制信号并振荡输出时钟。时钟分频器以预定速率分频输出时钟的频率，以产生反馈时钟。在PLL电路中，环路滤波器包括用于补偿变化的补偿器。

4. 发明授权

US07629833B2 Power supply apparatus of semiconductor integrated circuit 失效
标题翻译：半导体集成电路供电装置
公开(公告)号：US07629833B2
公开(公告)日：2009-12-08
申请号：US11822269
申请日：2007-07-03
申请人： Hyung-Soo Kim , Kun-Woo Park , Yong-Ju Kim , Ic-Su Oh , Hee-Woong Song , Jong-Woon Kim , Tae-Jin Hwang
发明人： Hyung-Soo Kim , Kun-Woo Park , Yong-Ju Kim , Ic-Su Oh , Hee-Woong Song , Jong-Woon Kim , Tae-Jin Hwang
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G06F1/28
摘要： A power supply apparatus of a semiconductor integrated circuit includes a power control device that detects a level of power supplied from the outside and outputs a control signal as information on the detected level, and a power supply device that controls an internal resistance component in response to an input of the control signal, controls the level of the power supplied from the outside, and supplies the power having the controlled level to circuit blocks.
摘要翻译：半导体集成电路的电源装置包括功率控制装置，其检测从外部供给的电力的电平，并输出作为关于检测电平的信息的控制信号;以及电源装置，其响应于控制信号的输入控制从外部提供的电力的电平，并将具有受控电平的电力提供给电路块。

5. 发明授权

US07646223B2 Phase locked loop circuit having set initial locking level and control method thereof 失效
标题翻译：具有设定初始锁定电平的锁相环电路及其控制方法
公开(公告)号：US07646223B2
公开(公告)日：2010-01-12
申请号：US11640965
申请日：2006-12-19
申请人： Yong-Ju Kim , Kun-Woo Park , Hyung-Soo Kim , Ic-Su Oh , Hee-Woong Song , Jong-Woon Kim , Tae-Jin Hwang
发明人： Yong-Ju Kim , Kun-Woo Park , Hyung-Soo Kim , Ic-Su Oh , Hee-Woong Song , Jong-Woon Kim , Tae-Jin Hwang
IPC分类号： H03L7/06
CPC分类号： H03L7/107 , H03L7/1075
摘要： A phase locked loop circuit and a control method thereof. A phase locked loop circuit includes a phase detecting and correcting block configured to detect a phase difference between a reference clock and a feedback clock, and to correct the phase of the feedback clock such that the phase of the reference clock and the phase of the feedback clock are consistent with each other, and an initial locking level setting block configured to set a locking level in a normal operation mode in the phase detecting and correcting block. The initial locking level setting block includes a digital-to-analog converting unit configured to generate an analog voltage according to a digital code corresponding to the set frequency, and charges the capacitive element with the analog voltage, and a switching unit configured to connect the digital-to-analog converting unit and the capacitive element in response to an input of an operation start signal.
摘要翻译：一种锁相环电路及其控制方法。锁相环电路包括相位检测和校正块，被配置为检测参考时钟和反馈时钟之间的相位差，并且校正反馈时钟的相位，使得参考时钟的相位和反馈的相位时钟彼此一致，并且初始锁定电平设置块被配置为在相位检测和校正块中将正常操作模式中的锁定电平设置为1。初始锁定电平设置块包括数模转换单元，被配置为根据与设定频率相对应的数字码产生模拟电压，并且用模拟电压对电容元件充电;以及开关单元，被配置为将数字模拟转换单元和电容元件，以响应于操作开始信号的输入。

6. 发明申请

US20070194818A1 Phase locked loop circuit having set initial locking level and control method thereof 失效
标题翻译：具有设定初始锁定电平的锁相环电路及其控制方法
公开(公告)号：US20070194818A1
公开(公告)日：2007-08-23
申请号：US11640965
申请日：2006-12-19
申请人： Yong-Ju Kim , Kun-Woo Park , Hyung-Soo Kim , Ic-Su Oh , Hee-Woong Song , Jong-Woon Kim , Tae-Jin Hwang
发明人： Yong-Ju Kim , Kun-Woo Park , Hyung-Soo Kim , Ic-Su Oh , Hee-Woong Song , Jong-Woon Kim , Tae-Jin Hwang
IPC分类号： H03L7/06
CPC分类号： H03L7/107 , H03L7/1075
摘要： A phase locked loop circuit and a control method thereof. A phase locked loop circuit includes a phase detecting and correcting block configured to detect a phase difference between a reference clock and a feedback clock, and to correct the phase of the feedback clock such that the phase of the reference clock and the phase of the feedback clock are consistent with each other, and an initial locking level setting block configured to set a locking level in a normal operation mode in the phase detecting and correcting block. The initial locking level setting block includes a digital-to-analog converting unit configured to generate an analog voltage according to a digital code corresponding to the set frequency, and charges the capacitive element with the analog voltage, and a switching unit configured to connect the digital-to-analog converting unit and the capacitive element in response to an input of an operation start signal.
摘要翻译：一种锁相环电路及其控制方法。锁相环电路包括相位检测和校正块，被配置为检测参考时钟和反馈时钟之间的相位差，并且校正反馈时钟的相位，使得参考时钟的相位和反馈的相位时钟彼此一致，并且初始锁定电平设置块被配置为在相位检测和校正块中将正常操作模式中的锁定电平设置为1。初始锁定电平设置块包括数模转换单元，被配置为根据与设定频率相对应的数字码产生模拟电压，并且用模拟电压对电容元件充电;以及开关单元，被配置为将数字模拟转换单元和电容元件，以响应于操作开始信号的输入。

7. 发明授权

US08013593B2 Voltage measuring apparatus for semiconductor integrated circuit and voltage measuring system having the same 有权
标题翻译：具有该半导体集成电路和电压测量系统的电压测量装置
公开(公告)号：US08013593B2
公开(公告)日：2011-09-06
申请号：US11961988
申请日：2007-12-20
申请人： Hyung-Soo Kim , Yong-Ju Kim , Jong-Woon Kim , Hee-Woong Song , Ic-Su Oh , Tae-Jin Hwang
发明人： Hyung-Soo Kim , Yong-Ju Kim , Jong-Woon Kim , Hee-Woong Song , Ic-Su Oh , Tae-Jin Hwang
IPC分类号： G01R25/00
CPC分类号： G01R31/3004 , G01R29/26
摘要： A voltage measuring apparatus for a semiconductor integrated circuit includes a first delay unit configured to delay a reference clock in a first region, a second delay unit configured to delay the reference clock in a second region and an analysis unit configured to analyze a difference in voltage level between the regions based on the phases of associated with the delayed clock signals generated by the first and second delay units.
摘要翻译：一种用于半导体集成电路的电压测量装置包括：第一延迟单元，被配置为延迟第一区域中的参考时钟;第二延迟单元，被配置为在第二区域中延迟参考时钟;以及分析单元，被配置为分析电压差基于与由第一延迟单元和第二延迟单元生成的延迟时钟信号相关联的相位，区域之间的电平。

8. 发明申请

US20090049686A1 Method of manufacturing component-embedded printed circuit board 有权
标题翻译：组件嵌入式印刷电路板的制造方法
公开(公告)号：US20090049686A1
公开(公告)日：2009-02-26
申请号：US12081858
申请日：2008-04-22
申请人： Hwa-Sun Park , Sung Yi , Sang-Chul Lee , Jong-Woon Kim , Yul-Kyo Chung
发明人： Hwa-Sun Park , Sung Yi , Sang-Chul Lee , Jong-Woon Kim , Yul-Kyo Chung
IPC分类号： H05K3/30
CPC分类号： H05K1/185 , H01L24/24 , H01L24/82 , H01L2224/24227 , H01L2224/92244 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H05K1/056 , H05K3/445 , H05K2201/0195 , H05K2201/0355 , H05K2201/0969 , H05K2203/1469 , Y10T29/43 , Y10T29/435 , Y10T29/49124 , Y10T29/49126 , Y10T29/4913 , Y10T29/49139
摘要： A method of manufacturing a component-embedded printed circuit board is disclosed. The method includes: forming a blind hole in the first metal layer such that the first insulation layer is exposed, for a metal-clad laminate that includes a first insulation layer stacked over a first metal layer, securing a component to the first insulation layer by embedding the component in the blind hole, stacking a second insulation layer and a second metal layer on either side of the metal-clad laminate, and forming circuit patterns by removing portions of the metal layers.
摘要翻译：公开了一种制造嵌入元件的印刷电路板的方法。该方法包括：在第一金属层上形成盲孔以使第一绝缘层暴露，对于包覆层叠在第一金属层上的第一绝缘层的覆金属层压板，将部件固定到第一绝缘层上将所述部件嵌入所述盲孔中，在所述覆金属层压板的任一侧堆叠第二绝缘层和第二金属层，以及通过去除所述金属层的一部分来形成电路图案。

9. 发明授权

US5684770A User table of contents data recovering method of a recordable optical disc driving apparatus 失效
标题翻译：可记录光盘驱动装置的用户目录数据恢复方法
公开(公告)号：US5684770A
公开(公告)日：1997-11-04
申请号：US565819
申请日：1995-12-01
申请人： Jong-Woon Kim
发明人： Jong-Woon Kim
IPC分类号： G11B19/04 , G11B27/034 , G11B27/11 , G11B27/32 , G11B19/02
CPC分类号： G11B19/04 , G11B27/034 , G11B27/11 , G11B27/329 , G11B2220/2529 , G11B2220/65
摘要： A method for recovering a user table of contents data for use by an optical disc driving apparatus which records data in a data record area of an optical disc. The method regenerates the data recorded in the data record area and records information relative to the regenerated data in the user table of contents data record area of the optical disc.
摘要翻译：一种用于恢复由光盘驱动装置使用的用户目录数据的方法，该光盘驱动装置将数据记录在光盘的数据记录区中。该方法重新记录在数据记录区中记录的数据，并且在光盘的内容数据记录区的用户表中记录与再生数据相关的信息。

10. 发明授权

US5706886A Finned tube heat exchanger 失效
标题翻译：翅片管换热器
公开(公告)号：US5706886A
公开(公告)日：1998-01-13
申请号：US666894
申请日：1996-08-01
申请人： Jong-Woon Kim
发明人： Jong-Woon Kim
IPC分类号： F28F1/32 , F28D1/04
CPC分类号： F28F1/325 , Y10T29/4938
摘要： A finned tube heat exchanger is disclosed in which the structure thereof is simple, and the heat exchanging performance is increased. The heat exchanger has a plurality of fin plates arranged in parallel with one another, and a plurality of heat exchanger tubes extending through the fin plates. Each of the fin plates has a plurality of projected strips, and the strips include first to ninth rows of strips disposed in a parallel relationship. Each of the first and ninth rows of strips is formed of a trapezoidal strip and two parallelogrammic strips, each of the second to eighth rows of strips is a strip extending between openings disposed adjacent to one another in the longitudinal direction of the fin plate. The second to eighth rows of strips are disposed not to be spaced, and two sides of each of the second to eighth rows of strips provided with leg portions are curved to have the same curvature as that of the openings adjacent to the two sides.
摘要翻译：公开了一种翅片管式热交换器，其结构简单，并且提高了热交换性能。热交换器具有彼此平行布置的多个翅片板，以及延伸穿过翅片板的多个热交换器管。每个鳍板具有多个突出的条，并且条带包括以平行关系设置的第一至第九行条。第一排和第九排条中的每一条由梯形条和两个平行四边形条形成，第二至第八行中的每一条是在翅板的纵向彼此相邻布置的开口之间延伸的条。第二到第八排的条被设置成不间隔，并且设置有腿部的第二到第八行的每一个的两个侧面被弯曲成具有与邻近两侧的开口相同的曲率。

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