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1. 发明申请

US20090011590A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20090011590A1
公开(公告)日：2009-01-08
申请号：US12136626
申请日：2008-06-10
申请人： Yong-Hwan RYU , Jun SEO , Eun-Young KANG , Jae-Seung HWANG , Sung-Un KWON
发明人： Yong-Hwan RYU , Jun SEO , Eun-Young KANG , Jae-Seung HWANG , Sung-Un KWON
IPC分类号： H01L21/4763
CPC分类号： H01L23/535 , H01L21/743 , H01L27/105 , H01L27/1052 , H01L27/11531 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a semiconductor device in which a plurality of conductive lines having a fine pitch and a uniform thickness can be formed is provided. The method includes forming a plurality of first conductive patterns in a insulation layer as closed curves, forming a plurality of mask patterns on the insulation layer, the mask patterns exposing end portions of each of the first conductive patterns, and forming a plurality of second conductive patterns in the insulation layer as lines by removing the end portions of each of the first conductive patterns.
摘要翻译：提供一种制造半导体器件的方法，其中可以形成具有细间距和均匀厚度的多条导线。该方法包括在绝缘层中形成多个第一导电图案作为闭合曲线，在绝缘层上形成多个掩模图案，掩模图案暴露出每个第一导电图案的端部，并且形成多个第二导电通过去除每个第一导电图案的端部，将绝缘层中的图案作为线。

2. 发明申请

US20110111532A1 METHODS OF FORMING PATTERN STRUCTURES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES USING THE SAME 有权
标题翻译：形成图案结构的方法和使用其制造半导体器件的方法
公开(公告)号：US20110111532A1
公开(公告)日：2011-05-12
申请号：US12940535
申请日：2010-11-05
申请人： Yong-Hwan RYU , Jae-Seung HWANG , Sung-Un KWON , Kyoung-Ha EOM
发明人： Yong-Hwan RYU , Jae-Seung HWANG , Sung-Un KWON , Kyoung-Ha EOM
IPC分类号： H01L43/12 , H01L21/34
CPC分类号： H01L43/12 , H01L27/228 , H01L27/2409 , H01L45/06 , H01L45/144 , H01L45/1675
摘要： Methods of forming pattern structures and methods of manufacturing memory devices using the same are provided, the methods of forming pattern structures include forming an etching object layer on a substrate and performing a plasma reactive etching process on the etching object layer using an etching gas including at least ammonia (NH3) gas. The etching object layer includes a magnetic material or a phase change material.
摘要翻译：提供了形成图案结构的方法和使用其制造存储器件的方法，形成图案结构的方法包括在衬底上形成蚀刻对象层，并使用包括在蚀刻对象层上的蚀刻气体对蚀刻对象层进行等离子体反应蚀刻处理最少氨（NH 3）气。蚀刻对象层包含磁性材料或相变材料。

3. 发明申请

US20070287287A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING CONTACT HOLE WITH HIGH ASPECT-RATIO 有权
标题翻译：具有高比例比例接触孔的半导体器件的制造方法
公开(公告)号：US20070287287A1
公开(公告)日：2007-12-13
申请号：US11759788
申请日：2007-06-07
申请人： Yun-Seung KANG , Jun SEO , Min-Chul CHAE , Jae-Seung HWANG , Sung-Un KWON , Woo-Jin CHO
发明人： Yun-Seung KANG , Jun SEO , Min-Chul CHAE , Jae-Seung HWANG , Sung-Un KWON , Woo-Jin CHO
IPC分类号： H01L21/44
CPC分类号： H01L27/11551 , H01L21/31144 , H01L21/743 , H01L27/0688 , H01L27/11526
摘要： Provided is a method of fabricating a semiconductor device having a contact hole with a high aspect-ratio. The method includes: sequentially forming a lower pattern and an upper layer on a semiconductor substrate; sequentially forming a lower mask layer and an upper mask layer on the upper layer; sequentially patterning the lower and upper mask layers to form a hole exposing a top surface of the upper layer on the lower pattern; using the upper mask layer as an etching mask to anisotropically etch the exposed top surface to form an upper contact hole exposing a top surface of the lower pattern; and using the lower mask layer as an etching mask to anisotropically etch the exposed lower pattern to form a lower contact hole in the lower pattern, the lower contact hole extending from the upper contact hole.
摘要翻译：提供一种制造具有高纵横比的接触孔的半导体器件的方法。该方法包括：在半导体衬底上依次形成下图案和上层; 在上层依次形成下掩模层和上掩模层; 顺序地图案化上下掩模层以形成暴露下图案上的上层的顶表面的孔; 使用上掩模层作为蚀刻掩模以各向异性地蚀刻暴露的顶表面以形成暴露下图案的顶表面的上接触孔; 并且使用下掩模层作为蚀刻掩模来各向异性蚀刻暴露的下图案以在下图案中形成下接触孔，下接触孔从上接触孔延伸。

4. 发明申请

US20090020816A1 SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME 审中-公开
标题翻译：半导体器件及其形成方法
公开(公告)号：US20090020816A1
公开(公告)日：2009-01-22
申请号：US12175364
申请日：2008-07-17
申请人： Woo-Jin CHO , Yong-Woo LEE , Jae-Seung HWANG , Sung-Un KWON , Min-Chul CHAE
发明人： Woo-Jin CHO , Yong-Woo LEE , Jae-Seung HWANG , Sung-Un KWON , Min-Chul CHAE
IPC分类号： H01L29/00
CPC分类号： H01L27/0688 , H01L21/8221
摘要： One embodiment generally described herein can be characterized as a semiconductor device. The semiconductor device can include a first transistor on a semiconductor substrate. A first interlayer insulating layer may be disposed over the first transistor and includes a first recess region. A single-crystalline semiconductor pattern may be disposed in the first recess region. A single-crystalline semiconductor plug may connect the semiconductor substrate to the single-crystalline semiconductor pattern. A second transistor may be disposed on the single-crystalline semiconductor pattern.
摘要翻译：本文通常描述的一个实施例可以被表征为半导体器件。半导体器件可以包括半导体衬底上的第一晶体管。第一层间绝缘层可以设置在第一晶体管的上方，并且包括第一凹部区域。单晶半导体图案可以设置在第一凹部区域中。单晶半导体插头可以将半导体衬底连接到单晶半导体图案。第二晶体管可以设置在单晶半导体图案上。

5. 发明申请

US20070141834A1 LOCAL INTERCONNECTION METHOD AND STRUCTURE FOR USE IN SEMICONDUCTOR DEVICE 失效
标题翻译：局部互连方法和结构用于半导体器件
公开(公告)号：US20070141834A1
公开(公告)日：2007-06-21
申请号：US11679722
申请日：2007-02-27
申请人： Sung-Un KWON , Yong-Sun KO
发明人： Sung-Un KWON , Yong-Sun KO
IPC分类号： H01L21/4763
CPC分类号： H01L21/76831 , H01L21/76807 , H01L21/76808 , H01L21/76895
摘要： A local interconnection wiring structure method for forming the same reduces the likelihood of a short between a local interconnection layer of gate electrodes and an active region by forming a common aperture so as to have a determined aperture between the local interconnection layer and the active region on an insulation film of a semiconductor substrate. Methods of forming the local interconnection wire can include forming a first etching mask pattern that has a size longer than a length between inner ends of adjacent gate electrodes formed on a semiconductor substrate and covered with an insulation film. The etching mask simultaneously has a length the same as or shorter than the length between outer ends of the gate electrodes. The insulation film exposed in the first etching mask pattern is subsequently etched so that the insulation film remains higher than a highest height of the gate electrodes, so as to form a recess pattern. The first etching mask pattern is then removed and a second etching mask pattern is formed so as to partially expose the insulation film provided within the recess pattern. The insulation film within the recess pattern is etched to form apertures for exposing a partial surface of the gate electrodes. The second etching mask pattern is then removed. The recess pattern and the apertures are then filled with conductive material to form a local interconnection layer for connecting between the gate electrodes.
摘要翻译：用于形成其的局部互连配线结构方法通过形成公共孔径来减小栅电极的局部互连层与有源区之间的短路的可能性，以便在局部互连层和有源区之间具有确定的孔径半导体衬底的绝缘膜。形成局部互连线的方法可以包括形成第一蚀刻掩模图案，其具有比形成在半导体衬底上并被绝缘膜覆盖的相邻栅电极的内端之间的长度的长度。蚀刻掩模同时具有与栅电极的外端之间的长度相同或更短的长度。随后蚀刻在第一蚀刻掩模图案中暴露的绝缘膜，使得绝缘膜保持高于栅电极的最高高度，以形成凹陷图案。然后去除第一蚀刻掩模图案，并且形成第二蚀刻掩模图案，以便部分地暴露设置在凹槽图案内的绝缘膜。蚀刻凹槽图形内的绝缘膜以形成用于暴露栅电极的局部表面的孔。然后去除第二蚀刻掩模图案。然后用导电材料填充凹槽图案和孔，以形成用于连接栅电极的局部互连层。

6. 发明申请

US20120273741A1 PHASE CHANGE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US20120273741A1
公开(公告)日：2012-11-01
申请号：US13443132
申请日：2012-04-10
申请人： Kyu-Man HWANG , Jun-Soo BAE , Sung-Un KWON , Kwang-Ho PARK
发明人： Kyu-Man HWANG , Jun-Soo BAE , Sung-Un KWON , Kwang-Ho PARK
IPC分类号： H01L47/00 , H01L21/02
CPC分类号： H01L45/06 , H01L27/2409 , H01L27/2463 , H01L45/1233 , H01L45/1683
摘要： A method of manufacturing a phase change memory device includes forming a lower electrode layer pattern and an insulating interlayer covering the lower electrode layer pattern, forming a first opening in the insulating interlayer to expose the lower electrode layer pattern, forming an oxide layer pattern on the sidewall of the first opening and a lower electrode under the oxide layer pattern by partially removing the oxide layer and the lower electrode layer pattern, forming an insulation layer filling a remaining portion of the first opening, removing the oxide layer pattern by a wet etching process to form a second opening, and forming a phase change material pattern on the lower electrode such that the phase change material pattern fills the second opening.
摘要翻译：一种制造相变存储器件的方法包括：形成下电极层图案和覆盖下电极层图案的绝缘夹层，在绝缘中间层中形成第一开口以露出下电极层图案，在其上形成氧化层图案通过部分地除去氧化物层和下部电极层图案，形成绝缘层，在第一开口的侧壁和下部电极的下方形成氧化物层图案，形成绝缘层，填充第一开口的剩余部分，通过湿蚀刻工艺去除氧化物层图案以形成第二开口，并且在下电极上形成相变材料图案，使得相变材料图案填充第二开口。

7. 发明申请

US20080088029A1 SEMICONDUCTOR DEVICE HAVING CONTACT BARRIER AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：具有接触障碍物的半导体器件及其制造方法
公开(公告)号：US20080088029A1
公开(公告)日：2008-04-17
申请号：US11933039
申请日：2007-10-31
申请人： Hyeong-Sun HONG , Jae-Goo LEE , Dong-Hyun KIM , Sung-Un KWON , Sang-Joon PARK , Nam-Jung KANG
发明人： Hyeong-Sun HONG , Jae-Goo LEE , Dong-Hyun KIM , Sung-Un KWON , Sang-Joon PARK , Nam-Jung KANG
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L27/0207 , H01L21/76802 , H01L27/10808 , H01L27/10855 , H01L27/10885 , Y10S257/905
摘要： A semiconductor device having a contact barrier for insulating contacts with a large aspect ratio and having a fine pitch between adjacent conductive lines and a method of manufacturing the same are provided. The semiconductor device includes a buried contact formed in a region between two adjacent first conductive lines and two adjacent second conductive lines. Insulating lines define a width of the buried contact. To form the contact barrier, an interlayer dielectric layer formed on the second conductive lines is patterned to form a space and an insulating line having an etching ratio different from the interlayer dielectric layer is formed in the space. The interlayer dielectric layer is selectively wet etched relative to an insulating layer covering the second conductive line and the first insulating line to form buried contact hole. The buried contact hole is filled with conductive material to form a buried contact.
摘要翻译：提供一种半导体器件，其具有用于具有大纵横比的绝缘触点的接触屏障，并且在相邻的导线之间具有微细的间距及其制造方法。半导体器件包括形成在两个相邻的第一导电线和两个相邻的第二导电线之间的区域中的掩埋接触。绝缘线限定埋入触点的宽度。为了形成接触屏障，形成在第二导线上的层间电介质层形成空间，并且在该空间中形成具有与层间电介质层不同的蚀刻比的绝缘线。相对于覆盖第二导线和第一绝缘线的绝缘层选择性地湿蚀刻层间电介质层以形成掩埋接触孔。埋入的接触孔填充有导电材料以形成掩埋接触。

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