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1. 发明申请

US20110267124A1 CLOCK SIGNAL DUTY CORRECTION CIRCUIT 有权
标题翻译：时钟信号校正电路
公开(公告)号：US20110267124A1
公开(公告)日：2011-11-03
申请号：US12846669
申请日：2010-07-29
申请人： Yong Ju KIM , Dae Han KWON , Won Joo YUN , Hae Rang CHOI , Jae Min JANG
发明人： Yong Ju KIM , Dae Han KWON , Won Joo YUN , Hae Rang CHOI , Jae Min JANG
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： A clock signal duty correction circuit includes: a first transition timing control unit configured to generate a first control signal for controlling a rising timing of a duty correction clock signal by using a clock signal; a second transition timing control unit configured to generate a second control signal for varying a falling timing of the duty correction clock signal by using the clock signal according to a code signal; and a differential buffer unit configured to generate the duty correction clock signal, whose rising time or falling time is adjusted, in response to the first control signal and the second control signal.
摘要翻译：时钟信号占空比校正电路包括：第一转移定时控制单元，被配置为通过使用时钟信号产生用于控制占空比校正时钟信号的上升定时的第一控制信号; 第二转移定时控制单元，被配置为通过使用根据代码信号的时钟信号来生成用于改变占空比校正时钟信号的下降定时的第二控制信号; 以及差分缓冲器单元，被配置为响应于所述第一控制信号和所述第二控制信号而生成其上升时间或下降时间被调整的占空比校正时钟信号。

2. 发明申请

US20110102035A1 SEMICONDUCTOR INTEGRATED CIRCUIT HAVING DELAY LOCKED LOOP CIRCUIT 有权
标题翻译：具有延迟锁定环路的半导体集成电路
公开(公告)号：US20110102035A1
公开(公告)日：2011-05-05
申请号：US12648380
申请日：2009-12-29
申请人： Hyun Woo LEE , Won Joo YUN
发明人： Hyun Woo LEE , Won Joo YUN
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/0805 , H03L7/095
摘要： A semiconductor integrated circuit is provided. The semiconductor integrated circuit includes: a delay locked loop (DLL) output block configured to delay an input clock signal by a predetermined time in response to a plurality of delay control signals and provide a DLL clock signal; a locking control block configured to compare a phase of a reference clock signal and a phase of a feedback clock signal, and synchronize the phase of the reference clock signal and the phase of the feedback clock signal in response to the plurality of delay control signals; and a locking detection block configured to detect whether the phase of the reference clock signal and the phase of the feedback clock signal are synchronized and the DLL clock signal is locked, wherein, when the DLL clock signal is locked, the locking control block provides the reference clock signal, which is obtained by dividing the input clock signal by n (where n is a natural number equal to or greater than 2), as an internal DLL clock signal.
摘要翻译：提供半导体集成电路。半导体集成电路包括：响应于多个延迟控制信号而将输入时钟信号延迟预定时间的延迟锁定环（DLL）输出块，并提供DLL时钟信号; 锁定控制块，被配置为比较参考时钟信号的相位和反馈时钟信号的相位，并且响应于所述多个延迟控制信号使参考时钟信号的相位和反馈时钟信号的相位同步; 以及锁定检测块，被配置为检测参考时钟信号的相位和反馈时钟信号的相位是否同步，并且DLL时钟信号被锁定，其中，当DLL时钟信号被锁定时，锁定控制块提供通过将输入时钟信号除以n（其中n是等于或大于2的自然数）获得的参考时钟信号作为内部DLL时钟信号。

3. 发明申请

US20120194231A1 POWER CONTROL CIRCUIT, METHOD OF CONTROLLING POWER CONTROL CIRCUIT, AND DLL CIRCUIT INCLUDING POWER CONTROL CIRCUIT 有权
标题翻译：功率控制电路，控制电路的控制方法以及包含功率控制电路的DLL电路
公开(公告)号：US20120194231A1
公开(公告)日：2012-08-02
申请号：US13442426
申请日：2012-04-09
申请人： Won Joo YUN , Hyun Woo LEE , Dong Suk SHIN
发明人： Won Joo YUN , Hyun Woo LEE , Dong Suk SHIN
IPC分类号： H03L7/08
CPC分类号： H03L7/0812
摘要： A method of controlling a power control circuit includes enabling a power cutoff signal when a delay locking operation of a Delay Locked Loop (DLL) circuit is completed, disabling the power cutoff signal for a predetermined time, and detecting a phase difference between a reference clock and a feedback clock to re-determine, on the basis of the detection result, whether or not to enable the power cutoff signal.
摘要翻译：一种控制功率控制电路的方法包括：当延迟锁定环路（DLL）电路的延迟锁定操作完成时，使能电源切断信号，在预定时间内禁用电源切断信号，并检测参考时钟以及反馈时钟，基于检测结果来重新确定是否启用电源切断信号。

4. 发明申请

US20120007646A1 DLL CIRCUIT HAVING ACTIVATION POINTS 有权
标题翻译：具有激活点的DLL电路
公开(公告)号：US20120007646A1
公开(公告)日：2012-01-12
申请号：US13237083
申请日：2011-09-20
申请人： Won Joo YUN , Hyun Woo LEE
发明人： Won Joo YUN , Hyun Woo LEE
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/0818
摘要： A delay locked loop (DLL) circuit includes a delay line configured to generate a delay clock signal by delaying a reference clock signal in response to a delay control signal, the delay line having two or more initial activation points, wherein the initial activation points are selected according to an initial value of the delay control signal; a delay compensating unit configured to generate a feedback clock signal by delaying the delay clock signal for a predetermined time; a phase detecting unit configured to generate a phase detection signal by comparing a phase of the reference clock signal to a phase of the feedback clock signal; and a delay control unit configured to generate the delay control signal in response to the phase detection signal.
摘要翻译：延迟锁定环路（DLL）电路包括延迟线，其被配置为通过响应于延迟控制信号延迟参考时钟信号来产生延迟时钟信号，该延迟线具有两个或多个初始激活点，其中初始激活点是根据延迟控制信号的初始值选择; 延迟补偿单元，被配置为通过将所述延迟时钟信号延迟预定时间来产生反馈时钟信号; 相位检测单元，被配置为通过将参考时钟信号的相位与反馈时钟信号的相位进行比较来产生相位检测信号; 以及延迟控制单元，被配置为响应于相位检测信号而产生延迟控制信号。

5. 发明申请

US20080001642A1 DELAY-LOCKED LOOP APPARATUS ADJUSTING INTERNAL CLOCK SIGNAL IN SYNCHRONIZATION WITH EXTERNAL CLOCK SIGNAL 审中-公开
标题翻译：延时锁定装置调节内部时钟信号与外部时钟信号同步
公开(公告)号：US20080001642A1
公开(公告)日：2008-01-03
申请号：US11683528
申请日：2007-03-08
申请人： Won Joo YUN , Hyun Woo LEE
发明人： Won Joo YUN , Hyun Woo LEE
IPC分类号： H03L7/00
CPC分类号： H03L7/0812 , H03L7/0818 , H03L7/087
摘要： A delay-locked loop apparatus includes at least a rising-clock delay-locked circuit, a falling-clock delay-locked circuit, and a duty cycle compensation circuit. The rising-clock delay-locked circuit detects the phase difference between a first clock inputted as a reference clock and a second clock obtained by replica-delaying the first clock, and then delay-locks the first clock and outputs a rising clock. The falling-clock delay-locked circuit detects the phase difference between an inverted clock of the first clock and the rising clock after a delay locking operation with respect to the rising clock, delay-locks an inverted clock of the first clock and outputs a falling clock. The duty cycle compensation circuit compensates duty cycles of the delay-locked rising clock and falling clock, and the falling-clock delay-locked circuit includes a divider for separately dividing the inverted clock and the delay-locked rising clock.
摘要翻译：延迟锁定环路装置至少包括上升时钟延迟锁定电路，下降时钟延迟锁定电路和占空比补偿电路。上升时钟延迟锁定电路检测作为参考时钟输入的第一时钟与通过复制延迟第一时钟而获得的第二时钟之间的相位差，然后延迟锁定第一时钟并输出上升时钟。下降时钟延迟锁定电路检测在相对于上升时钟的延迟锁定操作之后第一时钟的反相时钟和上升时钟之间的相位差，延迟锁定第一时钟的反相时钟并输出下降时钟。占空比补偿电路补偿延迟锁定上升时钟和下降时钟的占空比，下降时钟延迟锁定电路包括一个分频器，用于分开反相时钟和延迟锁定上升时钟。

6. 发明申请

US20110204951A1 SEMICONDUCTOR APPARATUS 失效
公开(公告)号：US20110204951A1
公开(公告)日：2011-08-25
申请号：US12843995
申请日：2010-07-27
申请人： Ki Han KIM , Hyun Woo LEE , Won Joo YUN
发明人： Ki Han KIM , Hyun Woo LEE , Won Joo YUN
IPC分类号： H03L5/00
CPC分类号： G11C5/147
摘要： A semiconductor apparatus for generating an internal voltage includes a control code output block and an internal voltage generation block. The control code output block is configured to output a variable code having a code value corresponding to a voltage level of an internal voltage. The internal voltage generation block is configured to compare the variable code to a setting code and controls the voltage level of the internal voltage according to the comparison.
摘要翻译：用于产生内部电压的半导体装置包括控制代码输出块和内部电压产生块。控制代码输出块被配置为输出具有与内部电压的电压电平对应的代码值的可变代码。内部电压生成块被配置为将可变代码与设置代码进行比较，并且根据比较来控制内部电压的电压电平。

7. 发明申请

US20100117695A1 SEMICONDUCTOR MEMORY APPARATUS 有权
公开(公告)号：US20100117695A1
公开(公告)日：2010-05-13
申请号：US12344799
申请日：2008-12-29
申请人： Hyun Woo LEE , Won Joo YUN
发明人： Hyun Woo LEE , Won Joo YUN
IPC分类号： H03L7/06
CPC分类号： H03L7/07 , H03L7/0812 , H03L7/0995 , H03L2207/06
摘要： A semiconductor memory apparatus having a clock signal generation circuit and a data output circuit is presented. The apparatus includes a delay locked loop (DLL), a phase locked loop (PLL), a frequency discrimination unit, and a data output buffer. The DLL circuit is configured to negatively delay a clock signal to generate a DLL clock signal. The PLL circuit is configured to receive the DLL clock signal to generate a control voltage in response to a frequency of the DLL clock signal and to generate a PLL clock signal of a frequency corresponding to a level of the control voltage. The frequency discrimination unit is configured to discriminate a frequency of the DLL clock signal in accordance with the level of the control voltage to generate a frequency discrimination signal. The data output buffer is configured to receive the DLL clock signal or the PLL clock signal to buffer output data signals.

8. 发明申请

US20100109725A1 DLL CIRCUIT HAVING DUTY CYCLE CORRECTION AND METHOD OF CONTROLLING THE SAME 失效
标题翻译：具有占空比校正的DLL电路及其控制方法
公开(公告)号：US20100109725A1
公开(公告)日：2010-05-06
申请号：US12345136
申请日：2008-12-29
申请人： Won Joo YUN , Hyun Woo LEE
发明人： Won Joo YUN , Hyun Woo LEE
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03K5/1565
摘要： A delay locked loop (DLL) circuit includes a duty cycle correcting unit configured to correct a duty cycle of a reference clock signal in response to a duty cycle correction signal and generate a correction clock signal. A feedback loop of the DLL circuit performs a delay lock operation on the correction clock signal and generates an output clock signal. A first duty cycle detecting unit detects a duty cycle of the correction clock signal and generates a first detection signal and a second duty cycle detecting unit detects a duty cycle of the output clock signal and generates a second detection signal. Finally, a duty cycle control unit generates the duty cycle correction signal in response to the first detection signal and the second detection signal to perform the duty cycle correction.
摘要翻译：延迟锁定环（DLL）电路包括占空比校正单元，其被配置为响应于占空比校正信号来校正参考时钟信号的占空比并产生校正时钟信号。 DLL电路的反馈回路对校正时钟信号执行延迟锁定操作，并产生输出时钟信号。第一占空比检测单元检测校正时钟信号的占空比并产生第一检测信号，第二占空比检测单元检测输出时钟信号的占空比并产生第二检测信号。最后，占空比控制单元响应于第一检测信号和第二检测信号产生占空比校正信号，以执行占空比校正。

9. 发明申请

US20110025390A1 UPDATE CONTROL APPARATUS IN DLL CIRCUIT 失效
标题翻译： DLL电路中的更新控制装置
公开(公告)号：US20110025390A1
公开(公告)日：2011-02-03
申请号：US12648516
申请日：2009-12-29
申请人： Won Joo YUN
发明人： Won Joo YUN
IPC分类号： H03L7/18
CPC分类号： H03L7/0814 , H03L7/0816
摘要： An update control apparatus in a DLL circuit is provided. The update control apparatus includes a logic value determination, a phase information collection unit, and an update control unit. The logic value determination unit is configured to determine a logic value of a phase detection signal for a first period interval of a reference clock signal to generate a phase information signal, and configured to extend the first period interval into a second period interval when an extension instruction signal is enabled. The phase information collection unit is configured to determine consecutive logic values of an update possible signal to generate the extension instruction signal, and configured to collect the phase information signal to generate an update information signal. The update control unit is configured to generate the update possible signal, a valid interval signal, and an update control signal in response to the update information signal.
摘要翻译：提供了DLL电路中的更新控制装置。更新控制装置包括逻辑值确定，相位信息收集单元和更新控制单元。逻辑值确定单元被配置为确定参考时钟信号的第一周期间隔的相位检测信号的逻辑值，以生成相位信息信号，并且被配置为当第一周期间隔延长到第二周期间隔时，指令信号被使能。相位信息收集单元被配置为确定更新可能信号的连续逻辑值以生成扩展指令信号，并且被配置为收集相位信息信号以生成更新信息信号。更新控制单元被配置为响应于更新信息信号而产生更新可能信号，有效间隔信号和更新控制信号。

10. 发明申请

US20110025384A1 DEVICE FOR GENERATING CLOCK IN SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：用于在半导体集成电路中产生时钟的器件
公开(公告)号：US20110025384A1
公开(公告)日：2011-02-03
申请号：US12646608
申请日：2009-12-23
申请人： Won Joo YUN , Hyun Woo Lee , Ki Han Kim
发明人： Won Joo YUN , Hyun Woo Lee , Ki Han Kim
IPC分类号： H03L7/06 , G06F1/04
CPC分类号： G06F1/06 , H03L7/0812 , H03L7/0995 , H03L7/16
摘要： Various embodiments of a semiconductor integrated circuit. According to one exemplary embodiment, a semiconductor integrated circuit includes a multi-phase clock generator that is configured to generate a multi-phase internal clock; a first edge combining unit that is configured to generate a first output clock having a first frequency by combining rising edges of clocks included in the internal clock, and transmit the first output clock to a first port; and a second edge combining unit that is configured to generate a second output clock having a second frequency by combining rising edges of clocks included in the internal clock, and transmit the output clock to a second port.
摘要翻译：半导体集成电路的各种实施例。根据一个示例性实施例，半导体集成电路包括被配置为产生多相内部时钟的多相时钟发生器; 第一边缘组合单元，被配置为通过组合包括在所述内部时钟中的时钟的上升沿来产生具有第一频率的第一输出时钟，并将所述第一输出时钟发送到第一端口; 以及第二边缘组合单元，其被配置为通过组合包括在所述内部时钟中的时钟的上升沿来产生具有第二频率的第二输出时钟，并将所述输出时钟发送到第二端口。

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