专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07750059B2 Polymer solution for nanoimprint lithography to reduce imprint temperature and pressure 失效
标题翻译：用于纳米压印光刻的聚合物溶液，以减少压印温度和压力
公开(公告)号：US07750059B2
公开(公告)日：2010-07-06
申请号：US10313596
申请日：2002-12-04
申请人： Gun Young Jung , Sivapackia Ganapathiappan , Yong Chen , R. Stanley Williams
发明人： Gun Young Jung , Sivapackia Ganapathiappan , Yong Chen , R. Stanley Williams
IPC分类号： B29C35/08
CPC分类号： B29C43/003 , B29C35/0888 , B29C59/022 , B29C2035/0827 , B29C2043/025 , B29C2059/023 , B82Y10/00 , B82Y40/00 , G03F7/0002 , G03F7/033
摘要： A method of forming features on substrates by imprinting is provided. The method comprises: (a) forming a polymer solution comprising at least one polymer dissolved in at least one polymerizable monomer; and (b) depositing the polymer solution on a substrate to form a liquid film thereon; and then either: (c) curing the liquid film by causing the monomer(s) to polymerize and optionally cross-linking the polymer(s) to thereby form a polymer film, the polymer film having a glass transition temperature (Tg); and imprinting the polymer film with a mold having a desired pattern to form a corresponding negative pattern in the polymer film, or (d) imprinting the liquid film with the mold and curing it to form the polymer film. The temperature of imprinting is as little as 10° C. above the Tg, or even less if the film is in the liquid state. The pressure of the imprinting can be within the range of 100 to 500 psi.
摘要翻译：提供了通过压印在基板上形成特征的方法。该方法包括：（a）形成包含至少一种溶解在至少一种可聚合单体中的聚合物的聚合物溶液; 和（b）将聚合物溶液沉积在基底上以在其上形成液膜; 然后：（c）通过使单体聚合并任选地交联聚合物从而形成聚合物膜来固化液膜，所述聚合物膜具有玻璃化转变温度（Tg）; 并用具有所需图案的模具印刷聚合物膜，以在聚合物膜中形成相应的负图案，或（d）用模具印刷液膜并固化以形成聚合物膜。压印温度比Tg高出10℃，或者如果薄膜处于液体状态，则其温度更低。压印的压力可以在100-500psi的范围内。

2. 发明授权

US07087946B2 Electric device having nanoscale wires and gaps 失效
标题翻译：具有纳米线和间隙的电器件
公开(公告)号：US07087946B2
公开(公告)日：2006-08-08
申请号：US10697589
申请日：2003-10-30
申请人： Yong Chen , R. Stanley Williams
发明人： Yong Chen , R. Stanley Williams
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/3081 , B82Y10/00 , G11C2213/81 , H01L21/3083 , H01L29/0665 , H01L29/0673 , H01L29/42312 , H01L29/66439 , Y10S438/945 , Y10S438/962 , Y10S977/888
摘要： A method for forming first and second linear structures of a first composition that meet at right angles, there being a gap at the point at which the structures meet. The linear structures are constructed on an etchable crystalline layer having the first composition. First and second self-aligned nanowires of a second composition are grown on this layer and used as masks for etching the layer. The self-aligned nanowires are constructed from a material that has an asymmetric lattice mismatch with respect to the crystalline layer. The gap is sufficiently small to allow one of the structures to act as the gate of a transistor and the other to form the source and drain of the transistor. The gap can be filled with electrically switchable materials thereby converting the transistor to a memory cell.
摘要翻译：一种用于形成第一组合物的第一和第二线性结构的方法，所述第一和第二线性结构垂直相交，在所述结构相交点处存在间隙。线性结构构造在具有第一组成的可蚀刻晶体层上。在该层上生长第二组合物的第一和第二自对准纳米线，并用作蚀刻该层的掩模。自对准纳米线由相对于晶体层具有不对称晶格失配的材料构成。该间隙足够小以允许一个结构用作晶体管的栅极，而另一个则形成晶体管的源极和漏极。间隙可以用电可切换材料填充，从而将晶体管转换成存储单元。

3. 发明授权

US06891744B2 Configurable nanoscale crossbar electronic circuits made by electrochemical reaction 有权
标题翻译：通过电化学反应制造的可配置的纳米级横梁电子电路
公开(公告)号：US06891744B2
公开(公告)日：2005-05-10
申请号：US10289703
申请日：2002-11-06
申请人： Yong Chen , R. Stanley Williams
发明人： Yong Chen , R. Stanley Williams
IPC分类号： G11C13/02 , G11C13/00 , H01L21/31 , H01L21/44
CPC分类号： G11C13/0009 , B82Y10/00 , G11C13/025 , G11C2213/34 , G11C2213/77 , G11C2213/81 , Y10S438/957 , Y10S977/936
摘要： Configurable electronic circuits comprise arrays of cross-points of one layer of metal/semiconductive nanoscale lines crossed by a second layer of metal/semiconductive nanoscale lines, with a configurable layer between the lines. Methods are provided for altering the thickness and/or resistance of the configurable layer by oxidation or reduction methods, employing a solid material as the configurable layer. Specifically a method is provided for configuring nanoscale devices in a crossbar array of configurable devices comprising arrays of cross-points of a first layer of nanoscale lines comprising a first metal or a first semiconductor material crossed by a second layer of nanoscale lines comprising a second metal or a second semiconductor material. The method comprises: (a) forming the first layer on a substrate; (b) forming a solid phase of a configurable material on the first layer at least in areas where the second layer is to cross the first layer; (c) forming the second layer on the configurable material, over the first layer; and (d) changing a property of the configurable material to thereby configure the nanoscale devices.
摘要翻译：可配置电子电路包括由第二层金属/半导体纳米级线交叉的一层金属/半导体纳米级线的交叉点阵列，其中线之间具有可配置层。提供了通过使用固体材料作为可配置层的氧化或还原方法来改变可配置层的厚度和/或电阻的方法。具体地，提供一种用于在可配置设备的交叉开关阵列中配置纳米级器件的方法，其包括第一纳米级线层的交点的阵列，其包括第一金属或第一半导体材料，所述第一金属或第一半导体材料由第二纳米级线交叉，所述第二金属或第二半导体材料包括第二金属或第二半导体材料。该方法包括：（a）在衬底上形成第一层; （b）至少在所述第二层与所述第一层交叉的区域中，在所述第一层上形成可配置材料的固相; （c）在所述可配置材料上形成在所述第一层上的所述第二层; 和（d）改变可配置材料的特性，从而配置纳米级器件。

4. 发明授权

US07803712B2 Multilevel imprint lithography 失效
公开(公告)号：US07803712B2
公开(公告)日：2010-09-28
申请号：US11636264
申请日：2006-12-07
申请人： Pavel Kornilovich , Yong Chen , Duncan Stewart , R. Stanley Williams , Philip J. Kuekes , Mehmet Fatih Yanik
发明人： Pavel Kornilovich , Yong Chen , Duncan Stewart , R. Stanley Williams , Philip J. Kuekes , Mehmet Fatih Yanik
IPC分类号： H01L21/308
CPC分类号： H01L21/76838 , B81C99/009 , B81C2201/0153 , B82Y10/00 , B82Y40/00 , G03F7/0002
摘要： A mold with a protruding pattern is provided that is pressed into a thin polymer film via an imprinting process. Controlled connections between nanowires and microwires and other lithographically-made elements of electronic circuitry are provided. An imprint stamp is configured to form arrays of approximately parallel nanowires which have (1) micro dimensions in the X direction, (2) nano dimensions and nano spacing in the Y direction, and three or more distinct heights in the Z direction. The stamp thus formed can be used to connect specific individual nanowires to specific microscopic regions of microscopic wires or pads. The protruding pattern in the mold creates recesses in the thin polymer film, so the polymer layer acquires the reverse of the pattern on the mold. After the mold is removed, the film is processed such that the polymer pattern can be transferred on a metal/semiconductor pattern on the substrate.

5. 发明授权

US07368395B2 Method for fabricating a nano-imprinting mold 失效
标题翻译：用于压印光刻及其制造的装置
公开(公告)号：US07368395B2
公开(公告)日：2008-05-06
申请号：US11601084
申请日：2006-11-16
申请人： M. Saif Islam , Gun Young Jung , Yong Chen , R. Stanley Williams
发明人： M. Saif Islam , Gun Young Jung , Yong Chen , R. Stanley Williams
IPC分类号： H01L21/461
CPC分类号： H01L21/76838 , H01L21/0337
摘要： An imprinting apparatus and method of fabrication provide a mold having a pattern for imprinting. The apparatus includes a semiconductor substrate polished in a [110] direction. The semiconductor substrate has a (110) horizontal planar surface and vertical sidewalls of a wet chemical etched trench. The sidewalls are aligned with and therefore are (111) vertical lattice planes of the semiconductor substrate. The semiconductor substrate includes a plurality of vertical structures between the sidewalls, wherein the vertical structures may be nano-scale spaced apart. The method includes wet etching a trench with spaced apart (111) vertical sidewalls in an exposed portion of the (110) horizontal surface of the semiconductor substrate along (111) vertical lattice planes. A chemical etching solution is used that etches the (111) vertical lattice planes slower than the (110) horizontal lattice plane. The method further includes forming the imprinting mold.
摘要翻译：压印装置和制造方法提供具有用于压印的图案的模具。该装置包括沿[110]方向抛光的半导体衬底。半导体衬底具有（110）水平平面和湿化学蚀刻沟槽的垂直侧壁。侧壁与半导体衬底对准并且因此是（111）垂直的晶格面。半导体衬底包括在侧壁之间的多个垂直结构，其中垂直结构可以是纳米级隔开的。该方法包括在（111）垂直晶格面的半导体衬底的（110）水平表面的暴露部分中湿式蚀刻具有间隔开（111）垂直侧壁的沟槽。使用蚀刻比（110）水平晶格面慢的（111）垂直晶格面的化学蚀刻溶液。该方法还包括形成压印模具。

6. 发明授权

US06699779B2 Method for making nanoscale wires and gaps for switches and transistors 失效
公开(公告)号：US06699779B2
公开(公告)日：2004-03-02
申请号：US10104348
申请日：2002-03-22
申请人： Yong Chen , R. Stanley Williams
发明人： Yong Chen , R. Stanley Williams
IPC分类号： H01L2144
CPC分类号： H01L21/3081 , B82Y10/00 , G11C2213/81 , H01L21/3083 , H01L29/0665 , H01L29/0673 , H01L29/42312 , H01L29/66439 , Y10S438/945 , Y10S438/962 , Y10S977/888
摘要： A method for forming first and second linear structures of a first composition that meet at right angles, there being a gap at the point at which the structures meet. The linear structures are constructed on an etchable crystalline layer having the first composition. First and second self-aligned nanowires of a second composition are grown on this layer and used as masks for etching the layer. The self-aligned nanowires are constructed from a material that has an asymmetric lattice mismatch with respect to the crystalline layer. The gap is sufficiently small to allow one of the structures to act as the gate of a transistor and the other to form the source and drain of the transistor. The gap can be filled with electrically switchable materials thereby converting the transistor to a memory cell.

7. 发明授权

US06656573B2 Method to grow self-assembled epitaxial nanowires 失效
标题翻译：生长自组装外延纳米线的方法
公开(公告)号：US06656573B2
公开(公告)日：2003-12-02
申请号：US10008058
申请日：2001-11-13
申请人： Yong Chen , R. Stanley Williams , Douglas A. A. Ohlberg
发明人： Yong Chen , R. Stanley Williams , Douglas A. A. Ohlberg
IPC分类号： C30B2910
CPC分类号： C30B23/02 , C30B25/02 , C30B29/605 , Y10S977/763 , Y10T428/12674 , Y10T428/24802 , Y10T428/24917 , Y10T428/24942 , Y10T428/249921
摘要： Self-assembled nanowires are provided, comprising nanowires of a first crystalline composition formed on a substrate of a second crystalline composition. The two crystalline materials are characterized by an asymmetric lattice mismatch, in which in the interfacial plane between the two materials, the first material has a close lattice match (in any direction) with the second material and has a large lattice mismatch in all other major crystallographic directions with the second material. This allows the unrestricted growth of the epitaxial crystal in the first direction, but limits the width in the other.
摘要翻译：提供了自组装的纳米线，其包括在第二结晶组合物的基底上形成的第一晶体组合物的纳米线。两种结晶材料的特征在于不对称晶格失配，其中在两种材料之间的界面中，第一种材料与第二种材料具有紧密的晶格匹配（在任何方向上），并且在所有其它主要材料中具有大的晶格失配晶体方向与第二种材料。这允许外延晶体在第一方向上的不受限制的生长，但是限制另一方的宽度。

8. 发明授权

US07404981B2 Printing electronic and opto-electronic circuits 有权
标题翻译：印刷电子和光电子电路
公开(公告)号：US07404981B2
公开(公告)日：2008-07-29
申请号：US10420565
申请日：2003-04-21
申请人： Xiao-An Zhang , R. Stanley Williams , Yong Chen
发明人： Xiao-An Zhang , R. Stanley Williams , Yong Chen
IPC分类号： B05D5/12 , C23C14/00
CPC分类号： H05K3/105 , H01L51/0004 , H01L51/0021 , H01L51/0037 , H05K3/02 , H05K2201/0329 , H05K2203/0108 , H05K2203/1142
摘要： A method is provided for printing electronic and opto-electronic circuits. The method comprises: (a) providing a substrate; (b) providing a film-forming precursor species; (c) forming a substantially uniform and continuous film of the film-forming precursor species on at least one side of the substrate, the film having a first electrical conductivity; and (d) altering portions of the film with at least one conductivity-altering species to form regions having a second electrical conductivity that is different than the first electrical conductivity, the regions thereby providing circuit elements. The method employs very simple and continuous processes, which make the time to produce a batch of circuits very short and leads to very inexpensive products, such as electronic memories (write once or rewriteable), electronically addressable displays, and generally any circuit for which organic electronics or opto-electronics are acceptable.
摘要翻译：提供了一种印刷电子和光电子电路的方法。该方法包括：（a）提供衬底; （b）提供成膜前体物质; （c）在所述基材的至少一侧上形成所述成膜前体物质的基本上均匀且连续的膜，所述膜具有第一导电性; 和（d）用至少一个导电性改变物质改变膜的部分，以形成具有不同于第一导电性的第二导电性的区域，由此提供电路元件。该方法采用非常简单和连续的过程，这使得生产一批电路非常短并且导致非常便宜的产品的时间，例如电子存储器（一次写入或可重写），电子寻址显示器，以及通常用于有机电子或光电子是可以接受的。

9. 发明授权

US07141866B1 Apparatus for imprinting lithography and fabrication thereof 失效
标题翻译：用于压印光刻及其制造的装置
公开(公告)号：US07141866B1
公开(公告)日：2006-11-28
申请号：US10826056
申请日：2004-04-16
申请人： M. Saif Islam , Gun Young Jung , Yong Chen , R. Stanley Williams
发明人： M. Saif Islam , Gun Young Jung , Yong Chen , R. Stanley Williams
IPC分类号： H01L29/04 , H01L31/036
CPC分类号： H01L21/76838 , H01L21/0337
摘要： An imprinting apparatus and method of fabrication provide a mold having a pattern for imprinting. The apparatus includes a semiconductor substrate polished in a [110] direction. The semiconductor substrate has a (110) horizontal planar surface and vertical sidewalls of a wet chemical etched trench. The sidewalls are aligned with and therefore are (111) vertical lattice planes of the semiconductor substrate. The semiconductor substrate includes a plurality of vertical structures between the sidewalls, wherein the vertical structures may be nano-scale spaced apart. The method includes wet etching a trench with spaced apart (111) vertical sidewalls in an exposed portion of the (110) horizontal surface of the semiconductor substrate along (111) vertical lattice planes. A chemical etching solution is used that etches the (111) vertical lattice planes slower than the (110) horizontal lattice plane. The method further includes forming the imprinting mold.
摘要翻译：压印装置和制造方法提供具有用于压印的图案的模具。该装置包括沿[110]方向抛光的半导体衬底。半导体衬底具有（110）水平平面和湿化学蚀刻沟槽的垂直侧壁。侧壁与半导体衬底对准并且因此是（111）垂直的晶格面。半导体衬底包括在侧壁之间的多个垂直结构，其中垂直结构可以是纳米级隔开的。该方法包括在（111）垂直晶格面的半导体衬底的（110）水平表面的暴露部分中湿式蚀刻具有间隔开（111）垂直侧壁的沟槽。使用蚀刻比（110）水平晶格面慢的（111）垂直晶格面的化学蚀刻溶液。该方法还包括形成压印模具。

10. 发明授权

US06773616B1 Formation of nanoscale wires 失效
标题翻译：纳米线的形成
公开(公告)号：US06773616B1
公开(公告)日：2004-08-10
申请号：US10033408
申请日：2001-12-26
申请人： Yong Chen , Douglas A. A. Ohlberg , Theodore I. Kamins , R. Stanley Williams
发明人： Yong Chen , Douglas A. A. Ohlberg , Theodore I. Kamins , R. Stanley Williams
IPC分类号： B44C122
CPC分类号： C30B23/02 , C30B25/02 , C30B29/605 , Y10S977/888
摘要： Self-organized, or self-assembled, nanowires of a first composition may be used as an etching mask for fabrication of nanowires of a second composition. The method for forming such nanowires comprises: (a) providing an etchable layer of the second composition and having a buried insulating layer beneath a major surface thereof; (b) growing self-assembled nanowires on the surface of the etchable layer; and (c) etching the etchable layer anisotropically down to the insulating layer, using the self-assembled nanowires as a mask. The self-assembled nanowires may be removed or left. In either event, nanowires of the second composition are formed. The method enables the formation of one-dimensional crystalline nanowires with widths and heights at the nanometer scale, and lengths at the micrometer scale, which are aligned along certain crystallographic directions with high crystal quality. Further, the method of the present invention avoids traditional lithography methods, minimizes environmental toxic chemicals usage, simplifies the manufacturing processes, and allows the formation of high-quality one-dimensional nanowires over large areas.
摘要翻译：可以将第一组合物的自组织或自组装的纳米线用作用于制造第二组合物的纳米线的蚀刻掩模。形成这种纳米线的方法包括：（a）提供第二组合物的可蚀刻层，并在其主表面下方具有掩埋绝缘层; （b）在可蚀刻层的表面上生长自组装纳米线; 和（c）使用自组装纳米线作为掩模，各向异性地将可蚀刻层蚀刻到绝缘层。自组装纳米线可以被去除或留下。在任一情况下，形成第二组合物的纳米线。该方法能够形成具有纳米尺度的宽度和高度的一维结晶纳米线，以及在具有高晶体质量的某些晶体方向上对准的微米尺度的长度。此外，本发明的方法避免了传统的光刻方法，使环境有毒化学品的使用最小化，简化了制造工艺，并且允许在大面积上形成高质量的一维纳米线。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式