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1. 发明授权

US06809479B2 Self-ballasted electrodeless discharge lamp and electrodeless discharge lamp operating device 失效
标题翻译：自镇流无电极放电灯和无电极放电灯操作装置
公开(公告)号：US06809479B2
公开(公告)日：2004-10-26
申请号：US10265047
申请日：2002-10-04
申请人： Yoko Shimomura , Koji Miyazaki , Satoshi Kominami , Kohei Enchi , Hiroyuki Uchiyama
发明人： Yoko Shimomura , Koji Miyazaki , Satoshi Kominami , Kohei Enchi , Hiroyuki Uchiyama
IPC分类号： H05B4116
CPC分类号： H01J65/048
摘要： A self-ballasted electrodeless discharge lamp of the invention is provided with a discharge vessel filled with discharge gas, the discharge vessel having a cavity portion, a coil inserted into the cavity portion of the discharge vessel, a ballast circuit for supplying high frequency power to the coil, and a lamp base that is electrically connected to the ballast circuit, wherein the discharge vessel, the coil, the ballast circuit, and the lamp base are configured as a single unit, and a reflective tape for reflecting light that is radiated from the discharge gas and emitted from inside the discharge vessel to its cavity portion side is wound around the coil.
摘要翻译：本发明的自镇流无电极放电灯设置有充满放电气体的放电容器，放电容器具有空腔部分，插入放电容器的空腔部分中的线圈，用于将高频电力提供给线圈和电连接到镇流器电路的灯座，其中放电容器，线圈，镇流器电路和灯座被配置为单个单元，以及用于反射从第放电气体从放电容器内部排出到其空腔部侧卷绕在线圈上。

2. 发明授权

US08183091B2 Semiconductor integrated circuit device and process for manufacturing the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US08183091B2
公开(公告)日：2012-05-22
申请号：US12757364
申请日：2010-04-09
申请人： Hiroyuki Uchiyama , Hiraku Chakihara , Teruhisa Ichise , Michimoto Kaminaga
发明人： Hiroyuki Uchiyama , Hiraku Chakihara , Teruhisa Ichise , Michimoto Kaminaga
IPC分类号： H01L23/544 , H01L21/304
CPC分类号： H01L23/544 , G03F9/7076 , H01L21/30625 , H01L21/31053 , H01L21/76229 , H01L21/76819 , H01L21/78 , H01L22/34 , H01L23/585 , H01L27/0207 , H01L29/78 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor IC includes grooves formed in a substrate to define a first dummy region and second dummy regions formed at a scribing area, and third dummy regions and a fourth dummy region formed at a product area. A width of the first dummy region is greater than widths of each of the second and third dummy regions and a width of the fourth dummy region is greater than widths of each of the third dummy regions. A conductor pattern is formed over the first dummy region for optical pattern recognition. The first dummy region is formed under the conductor pattern so the grooves are not formed under the conductor pattern. The second dummy regions are spaced from one another by a predetermined spacing at the scribing area, and the third dummy regions are spaced from one another by a predetermined spacing at the product area.
摘要翻译：半导体IC包括形成在基板中的槽，用于限定形成在划线区域的第一虚拟区域和第二虚拟区域，以及形成在产品区域的第三虚拟区域和第四虚拟区域。第一虚拟区域的宽度大于第二和第三虚拟区域中的每一个的宽度，并且第四虚拟区域的宽度大于每个第三虚拟区域的宽度。在第一虚拟区域上形成用于光学图案识别的导体图案。第一虚拟区域形成在导体图案下方，使得沟槽不形成在导体图案之下。第二虚拟区域在划刻区域处以预定间隔彼此间隔开，并且第三虚拟区域在产品区域处彼此间隔开预定间隔。

3. 发明授权

US08013373B2 Semiconductor device having MOS-transistor formed on semiconductor substrate and method for manufacturing thereof 有权
标题翻译：具有形成在半导体衬底上的MOS晶体管的半导体器件及其制造方法
公开(公告)号：US08013373B2
公开(公告)日：2011-09-06
申请号：US12361117
申请日：2009-01-28
申请人： Hiroyuki Uchiyama
发明人： Hiroyuki Uchiyama
IPC分类号： H01L27/108
CPC分类号： H01L27/0207 , H01L21/823437 , H01L27/10814 , H01L27/10855 , H01L27/10876 , H01L27/10888 , H01L27/10891
摘要： A semiconductor device comprises MOS transistors sequentially arranged in the plane direction of a substrate, wherein a gate electrode and a wiring portion for connecting between the gate electrodes to each other are implanted into a layer that is lower than a surface of the substrate in which a diffusion layer has been formed. A first device isolation area with a STI structure for separating the diffusion layers that function as a source/drain area is formed on the surface of the substrate. A second device isolation area with the STI structure for separating channel areas of the MOS transistors adjacent to each other is formed in a layer that is lower than a layer that has the first device isolation area.
摘要翻译：半导体器件包括依次布置在衬底的平面方向上的MOS晶体管，其中用于将栅电极彼此连接的栅电极和布线部分被注入到低于衬底表面的层中，其中，扩散层已经形成。在基板的表面上形成具有用于分离用作源极/漏极区域的扩散层的STI结构的第一器件隔离区域。具有用于分离相邻的MOS晶体管的沟道区域的STI结构的第二器件隔离区域形成在低于具有第一器件隔离区域的层的层中。

4. 发明申请

US20110081655A1 NUCLEIC ACID ANALYZING DEVICE AND NUCLEIC ACID ANALYZER 有权
标题翻译：核酸分析装置和核酸分析仪
公开(公告)号：US20110081655A1
公开(公告)日：2011-04-07
申请号：US12997469
申请日：2009-05-13
申请人： Masatoshi Narahara , Toshiro Saito , Naoshi Itabashi , Jiro Yamamoto , Hiroyuki Uchiyama
发明人： Masatoshi Narahara , Toshiro Saito , Naoshi Itabashi , Jiro Yamamoto , Hiroyuki Uchiyama
IPC分类号： C12Q1/68 , C12M1/34
CPC分类号： G01N21/648
摘要： An object of the present invention relates to distinguishing, from a fluorophore of an unreacted substrate, a single fluorophore attached to a nucleotide that is incorporated into a probe by a nucleic acid synthesis. The present invention relates to a nucleic acid analyzing device that analyzes a nucleic acid in sample by fluorescence, wherein a localized surface plasmon is generated by illumination, and a probe for analyzing the nucleic acid in the sample is on the site where the surface plasmon is generated. According to the present invention, since it is possible to efficiently produce fluorescence intensifying effects due to the surface plasmon and to immobilize the probe to a region within the reach of the fluorescence intensifying effects, it becomes possible to measure a nucleic acid synthesis without removing unreacted nucleotide to which fluorophores are attached.
摘要翻译：本发明的目的在于从未反应的底物的荧光团区分与通过核酸合成并入探针中的核苷酸连接的单个荧光团。本发明涉及通过荧光分析样品中的核酸的核酸分析装置，其中通过照射产生局部表面等离子体激元，并且用于分析样品中的核酸的探针位于表面等离子体为生成。根据本发明，由于可以有效地产生由于表面等离子体激元引起的荧光增强作用并且将探针固定在荧光增强作用范围内的区域，因此可以测量核酸合成而不去除未反应的附着有荧光团的核苷酸。

5. 发明授权

US07816702B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07816702B2
公开(公告)日：2010-10-19
申请号：US12245077
申请日：2008-10-03
申请人： Shinichi Saito , Masahiro Aoki , Hiroyuki Uchiyama , Hideo Arimoto , Noriyuki Sakuma , Jiro Yamamoto
发明人： Shinichi Saito , Masahiro Aoki , Hiroyuki Uchiyama , Hideo Arimoto , Noriyuki Sakuma , Jiro Yamamoto
IPC分类号： H01L33/00
CPC分类号： H01S5/12 , B82Y20/00 , H01S5/0424 , H01S5/0425 , H01S5/1237 , H01S5/125 , H01S5/18341 , H01S5/3004 , H01S5/3427 , H01S2301/176 , H01S2302/00
摘要： There are a silicon laser device having a IV-group semiconductor such as silicon or germanium equivalent to the silicon as a basic constituent element on a substrate made of the silicon, and the like by a method capable of easily forming the silicon laser device by using a general silicon process, and a manufacturing method thereof. The silicon laser device is an ultrathin silicon laser that includes a first electrode unit injecting electrons, a second electrode unit injecting holes, a light emitting unit electrically connected to the first electrode unit and the second electrode unit, wherein the light emitting unit is made of single-crystal silicon and has a first surface (top surface) and a second surface (bottom surface) opposed to the first surface, a waveguide made of a first dielectric, which is disposed in the vicinity of the light emitting unit, by setting surface directions of the first and second surfaces as a surface (100) and thinning a thickness of the light emitting unit in a direction perpendicular to the first and second surfaces, and a mirror formed by alternately adjoining the first dielectric and a second dielectric.
摘要翻译：存在具有诸如硅等离子体的硅组合半导体的硅激光器装置，其等同于由硅制成的衬底上作为基本构成元件的硅等，通过使用能够容易地形成硅激光器件的方法，通用硅工艺及其制造方法。硅激光器件是一种超薄硅激光器，其包括注入电子的第一电极单元，注入空穴的第二电极单元，与第一电极单元和第二电极单元电连接的发光单元，其中发光单元由单晶硅，并且具有与第一表面相对的第一表面（顶表面）和第二表面（底表面），通过设置在发光单元附近的由第一电介质制成的波导第一表面和第二表面的方向作为表面（100），并且在垂直于第一和第二表面的方向上减薄发光单元的厚度，以及通过交替地邻接第一电介质和第二电介质而形成的反射镜。

6. 发明申请

US20100237397A1 Semiconductor memory device and manufacturing method thereof 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20100237397A1
公开(公告)日：2010-09-23
申请号：US12659563
申请日：2010-03-12
申请人： Hiroyuki Uchiyama
发明人： Hiroyuki Uchiyama
IPC分类号： H01L27/108
CPC分类号： H01L27/10876 , H01L29/66666 , H01L29/7827
摘要： To provide an active region having first and second diffusion layers positioned at both sides of a gate trench and a third diffusion layer formed on a bottom surface of the gate trench, first and second memory elements connected to the first and second diffusion layers, respectively, a bit line connected to the third diffusion layer, a first gate electrode that covers a first side surface of the gate trench via a gate dielectric film and forms a channel between the first diffusion layer and the third diffusion layer, and a second gate electrode that covers a second side surface of the gate trench via a gate dielectric film and forms a channel between the second diffusion layer and the third diffusion layer. According to the present invention, because separate transistors are formed on both side surfaces of a gate trench, two times of conventional integration can be achieved.
摘要翻译：为了提供具有位于栅极沟槽的两侧的第一和第二扩散层和形成在栅极沟槽的底表面上的第三扩散层的有源区，分别连接到第一和第二扩散层的第一和第二存储元件，连接到所述第三扩散层的位线，经由栅极电介质膜覆盖所述栅极沟槽的第一侧表面并在所述第一扩散层和所述第三扩散层之间形成沟道的第一栅电极，以及第二栅电极，经由栅极电介质膜覆盖栅极沟槽的第二侧表面，并在第二扩散层和第三扩散层之间形成通道。根据本发明，由于在栅极沟槽的两个侧表面上形成分离的晶体管，所以可以实现两次常规集成。

7. 发明申请

US20100140614A1 OXIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME AND ACTIVE MATRIX SUBSTRATE 失效
标题翻译：氧化物半导体器件及其制造方法和有源矩阵衬底
公开(公告)号：US20100140614A1
公开(公告)日：2010-06-10
申请号：US12633577
申请日：2009-12-08
申请人： Hiroyuki Uchiyama , Tetsufumi Kawamura , Hironori Wakana
发明人： Hiroyuki Uchiyama , Tetsufumi Kawamura , Hironori Wakana
IPC分类号： H01L29/24 , H01L21/36
CPC分类号： H01L29/7869 , H01L21/02554 , H01L21/02565 , H01L21/02617 , H01L21/28291 , H01L27/10873 , H01L27/112 , H01L27/11206 , H01L27/1225 , H01L27/3262 , H01L51/5206
摘要： A phenomenon of change of a contact resistance between an oxide semiconductor and a metal depending on an oxygen content ratio in introduced gas upon depositing an oxide semiconductor film made of indium gallium zinc oxide, zinc tin oxide, or others in an oxide semiconductor thin-film transistor. A contact layer is formed with an oxygen content ratio of 10% or higher in a region from a surface, where the metal and the oxide semiconductor are contacted, down to at least 3 nm deep in depth direction, and a region to be a main channel layer is further formed with an oxygen content ratio of 10% or lower, so that a multilayered structure is formed, and both of ohmic characteristics to the electrode metal and reliability such as the suppression of threshold potential shift are achieved.
摘要翻译：在氧化物半导体薄膜中沉积由铟镓锌氧化物，氧化锌锡等制成的氧化物半导体膜时，导入气体中的氧含量比的氧化物半导体与金属之间的接触电阻发生变化的现象晶体管。在从金属和氧化物半导体接触的表面的区域的氧含量比为10％以上形成接触层，深度为深度至少3nm以下的区域进一步形成具有10％或更低的氧含量比的沟道层，从而形成多层结构，并且实现了与电极金属的欧姆特性和诸如抑制阈值电位移动之类的可靠性。

8. 发明授权

US07732273B2 Semiconductor device manufacturing method and semiconductor device 失效
标题翻译：半导体器件制造方法和半导体器件
公开(公告)号：US07732273B2
公开(公告)日：2010-06-08
申请号：US12213624
申请日：2008-06-23
申请人： Hiroyuki Uchiyama
发明人： Hiroyuki Uchiyama
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L28/40 , H01L27/10852
摘要： A manufacturing method of a semiconductor device having a highly reliable capacitor, and the semiconductor device are provided. The semiconductor device manufacturing method according to the present invention includes: a first step of forming a first electrode of a capacitor on a semiconductor substrate; a second step of forming a capacitor insulating film on the whole surface including a side surface and an upper surface of the first electrode; a third step of forming a protection insulating film made of a material different from that of the capacitor insulating film, on the capacitor insulating film; a fourth step of removing the protection insulating film and the capacitor insulating film from the upper surface of the first electrode, by anisotropically etching the protection insulating film and the capacitor insulating film; a fifth step of removing the protection insulating film that remains on the side surface of the first electrode; and a sixth step of forming a second electrode of the capacitor on the capacitor insulating film, after removing the protection insulating film.
摘要翻译：提供具有高可靠性电容器的半导体器件的制造方法和半导体器件。根据本发明的半导体器件制造方法包括：在半导体衬底上形成电容器的第一电极的第一步骤; 在包括第一电极的侧表面和上表面的整个表面上形成电容器绝缘膜的第二步骤; 在电容器绝缘膜上形成由不同于电容器绝缘膜的材料制成的保护绝缘膜的第三步骤; 通过各向异性蚀刻保护绝缘膜和电容器绝缘膜，从第一电极的上表面去除保护绝缘膜和电容器绝缘膜的第四步骤; 去除保留在第一电极的侧表面上的保护绝缘膜的第五步骤; 以及在除去保护绝缘膜之后，在电容器绝缘膜上形成电容器的第二电极的第六步骤。

9. 发明申请

US20090261325A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090261325A1
公开(公告)日：2009-10-22
申请号：US12423053
申请日：2009-04-14
申请人： Tetsufumi Kawamura , Takeshi Sato , Mutsuko Hatano , Hiroyuki Uchiyama
发明人： Tetsufumi Kawamura , Takeshi Sato , Mutsuko Hatano , Hiroyuki Uchiyama
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L27/1225 , H01L27/1214 , H01L27/127 , H01L29/7869
摘要： A metallic oxide semiconductor device with high performance and small variations. It is a field effect transistor using a metallic oxide film for the channel, which includes a channel region and a source region and comprises a drain region with a lower oxygen content than the channel region in the metallic oxide, in which the channel region exhibits semiconductor characteristics and the oxygen content decreases with depth below the surface.
摘要翻译：具有高性能和小变化的金属氧化物半导体器件。它是一种使用金属氧化物膜作为沟道的场效应晶体管，其包括沟道区和源极区，并且包括具有比金属氧化物中的沟道区更低的氧含量的漏区，其中沟道区表现出半导体特性和氧含量随着表面深度的减小而减小。

10. 发明申请

US20090121283A1 Semiconductor device and fabrication method of the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090121283A1
公开(公告)日：2009-05-14
申请号：US12289372
申请日：2008-10-27
申请人： Hiroyuki Uchiyama
发明人： Hiroyuki Uchiyama
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/78642 , H01L27/12
摘要： A semiconductor device includes a substrate; a first insulating layer provided on the substrate; a conductive layer buried in the first insulating layer; a semiconductor pillar including a lower diffusion layer provided immediately above the conductive layer, the lower diffusion layer being electrically connected to the conductive layer, a semiconductor layer on the lower diffusion layer, and an upper diffusion layer on the semiconductor layer; a gate insulating film provided on a peripheral side surface of the semiconductor layer; a gate electrode provided on the gate insulating film; and a second insulating layer provided such that the gate electrode and a circumference of the semiconductor pillar are buried in the second insulating layer.
摘要翻译：半导体器件包括衬底; 设置在所述基板上的第一绝缘层; 埋入第一绝缘层中的导电层; 半导体柱，包括紧邻导电层上方的下扩散层，下扩散层与导电层电连接，下扩散层上的半导体层和半导体层上的上扩散层; 设置在所述半导体层的周边侧面上的栅极绝缘膜; 设置在所述栅极绝缘膜上的栅电极; 以及设置成使得栅电极和半导体柱的周边被埋在第二绝缘层中的第二绝缘层。

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