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1. 发明授权

US5036424A Multilayer ceramic capacitive element 失效
标题翻译：多层陶瓷电容元件
公开(公告)号：US5036424A
公开(公告)日：1991-07-30
申请号：US525024
申请日：1990-05-18
申请人： Yoichiro Yokotani , Hiroshi Kagata , Junichi Kato , Seiichi Nakatani , Yukio Terada
发明人： Yoichiro Yokotani , Hiroshi Kagata , Junichi Kato , Seiichi Nakatani , Yukio Terada
IPC分类号： B32B18/00 , H01G4/12
CPC分类号： B32B18/00 , C04B35/465 , C04B35/4688 , C04B35/472 , C04B35/497 , C04B35/6262 , H01G4/1209 , H01G4/1227 , H01G4/1254 , C04B2235/3206 , C04B2235/3208 , C04B2235/3213 , C04B2235/3258 , C04B2235/3279 , C04B2235/3281 , C04B2235/3284 , C04B2235/5445 , C04B2235/652 , C04B2235/6562 , C04B2235/6565 , C04B2235/6567 , C04B2235/6584 , C04B2235/79 , C04B2237/345 , C04B2237/346 , C04B2237/68 , C04B2237/704 , Y10T29/435
摘要： A multilayer ceramic capacitor comprises plural ceramic dielectric layers laminated one on another, and at least two internal electrodes separated by the ceramic dielectric layer and alternately terminated at the opposite sides of the laminated ceramic dielectric layers. The ceramic dielectric layers is composed of a complex oxide including a component (A), a component (B) and copper, wherein the component (A), is at least one element selected from the group consisting of Pb, Ca, Sr and Ba, but contains Pb at the least, wherein the component (B) is at least two elements selected from the group consisting of Mg, Ni, Zn, Ti, Ta, Nb and W, the molar ratio of the component (A) to component (B) being not less than 0.985, but not more than 1.110, and wherein the content of said copper in the complex oxide is more than 0.650 wt %, but not more than 2.200 wt % in terms of Cu.sub.2 O. The internal electrodes are composed of copper or an alloy mainly comprising copper.
摘要翻译：多层陶瓷电容器包括彼此层叠的多个陶瓷电介质层和由陶瓷电介质层隔开的至少两个内部电极，并且交替地端接在层叠陶瓷电介质层的相对侧。陶瓷电介质层由包含组分（A），组分（B）和铜的复合氧化物组成，其中组分（A）为选自Pb，Ca，Sr和Ba中的至少一种元素，但含有Pb，其中组分（B）为选自Mg，Ni，Zn，Ti，Ta，Nb和W中的至少两种元素，组分（A）与组分（B）不小于0.985，但不大于1.110，并且其中复合氧化物中所述铜的含量以Cu 2 O计大于0.650重量％，但不大于2.200重量％。内部电极由铜或主要包含铜的合金组成。

2. 发明授权

US5128827A Electronic devices, method for forming end terminations thereof and paste material for forming same 失效
标题翻译：电子器件，其端部端部的形成方法和用于形成端部端子的糊状材料
公开(公告)号：US5128827A
公开(公告)日：1992-07-07
申请号：US671930
申请日：1991-03-20
申请人： Yoichiro Yokotani , Seiichi Nakatani , Koichi Kugimiya
发明人： Yoichiro Yokotani , Seiichi Nakatani , Koichi Kugimiya
IPC分类号： H01C1/142 , H01G4/232 , H01R13/03
CPC分类号： H01G4/2325 , H01C1/142 , H01R13/03 , Y10T29/435
摘要： An improved electronic device having metal-glazing type end terminations comprising a surface metal phase of Sn or Zn, is produced by sintering a paste material containing a matrix metal powder (Cu and/or Ni), a fluxing metal powder and an organic binding material, so that the surface portion serves to improve wettability and solderability of the end termination owing to its composition being similar to solder.
摘要翻译：通过烧结含有基质金属粉末（Cu和/或Ni），助熔金属粉末和有机粘合材料的糊料，制造具有金属玻璃型端部末端的改进的电子器件，其包括Sn或Zn的表面金属相，使得表面部分由于其组成类似于焊料而用于改善端部端接件的润湿性和可焊性。

3. 发明授权

US5004640A Multilayered ceramic substrates and method for manufacturing the same 失效
标题翻译：多层陶瓷基板及其制造方法
公开(公告)号：US5004640A
公开(公告)日：1991-04-02
申请号：US321702
申请日：1989-03-10
申请人： Seiichi Nakatani , Satoru Yuhaku , Tsutomu Nishimura , Yukio Terada , Yasuyuki Baba
发明人： Seiichi Nakatani , Satoru Yuhaku , Tsutomu Nishimura , Yukio Terada , Yasuyuki Baba
IPC分类号： H05K3/46 , B32B18/00 , C04B35/18 , C04B35/634 , C04B35/636 , H01L21/48 , H01L23/15 , H05K1/03
CPC分类号： C04B35/63416 , B32B18/00 , C04B35/18 , C04B35/634 , C04B35/6342 , C04B35/63424 , C04B35/6365 , H01L21/4857 , H01L23/15 , H05K1/0306 , C04B2237/34 , H01L2924/0002 , H01L2924/09701 , H05K3/4629 , Y10S428/901 , Y10T428/24802 , Y10T428/24917 , Y10T428/24926
摘要： Multilayered ceramic substrates having Cu electrode patterns in or on ceramic-glass insulating layers which consist essentially of Al.sub.2 O.sub.3, SiO.sub.2, B.sub.2 O.sub.3, Na.sub.2 O, K.sub.2 O, CaO, MgO and PbO. The methods for manufacturing the substrate comprises thermally treating a laminate of alternately superimposing ceramic-glass insulating layers and CuO-based electrode layers of desired patterns in air or in a molecular oxygen-containing atmosphere to eliminate organic binders from the laminates by burning out, reducing the CuO into metallic Cu at low temperatures in an atmosphere containing hydrogen, and firing the thus reduced laminate in an inert gas such as nitrogen. The firing is effected at 850.degree. to 950.degree. C. The multilayered ceramic substrate may also be obtained by forming ceramic-glass insulating layers and CuO-based electrode layers alternately on a sintered ceramic support, followed by the thermal treatment, reduction and firing set forth above.

4. 发明授权

US06392525B1 Magnetic element and method of manufacturing the same 有权
标题翻译：磁性元件及其制造方法
公开(公告)号：US06392525B1
公开(公告)日：2002-05-21
申请号：US09472252
申请日：1999-12-27
申请人： Junichi Kato , Osamu Inoue , Seiichi Nakatani , Koichi Hirano , Toshiyuki Asahi
发明人： Junichi Kato , Osamu Inoue , Seiichi Nakatani , Koichi Hirano , Toshiyuki Asahi
IPC分类号： H01F2724
CPC分类号： H01F27/022 , H01F3/08 , H01F27/34 , H01F2017/048
摘要： A magnetic element including: a composite magnetic member A containing a metallic magnetic powder in an amount of 50-70 vol. % and a thermosetting resin in an amount of 50-30 vol. %; a magnetic member B that is at least one selected from a ferrite sintered body and a pressed-powder magnetic body of a metallic magnetic powder; and a coil. The magnetic element is characterized in that a magnetic path determined by an arrangement of the coil passes the magnetic member A and the magnetic member B in series and the coil is embedded in the magnetic member A. The present invention also provides a method for manufacturing the magnetic element.
摘要翻译：一种磁性元件，包括：含有50-70体积％的金属磁性粉末的复合磁性体A。％和热固性树脂，其量为50-30vol。％; 磁性体B，其是选自铁氧体烧结体和金属磁性粉末的压粉体磁体中的至少一种; 和线圈。磁性元件的特征在于，由线圈的布置确定的磁路通过磁性构件A和磁性构件B串联，并且线圈被嵌入在磁性构件A中。本发明还提供了一种用于制造磁性元件。

5. 发明授权

US08435842B2 Method for manufacturing flexible semiconductor device 有权
标题翻译：柔性半导体器件的制造方法
公开(公告)号：US08435842B2
公开(公告)日：2013-05-07
申请号：US12681399
申请日：2009-07-30
申请人： Koichi Hirano , Seiichi Nakatani , Tatsuo Ogawa
发明人： Koichi Hirano , Seiichi Nakatani , Tatsuo Ogawa
IPC分类号： H01L21/00
CPC分类号： H01L51/0541 , H01L51/0004 , H01L51/0022 , H01L51/0097 , H01L51/107 , Y02E10/549 , Y02P70/521
摘要： A method for manufacturing a flexible semiconductor device comprises (i) forming an insulating film on the upper surface of a resin film, (ii) forming a pattern of extraction electrodes on the upper surface of the resin film, (iii) forming a semiconductor layer on the insulating film in such a manner that the semiconductor layer is in contact with the pattern of extraction electrodes, and (iv) forming a sealing resin layer on the upper surface of the resin film in such a manner that the sealing resin layer covers the semiconductor layer and the pattern of extraction electrodes, wherein at least one of the stepsof the above steps (i) to (iv) is carried out by a printing method. With this manufacturing method, various layers can be formed by a simple printing process without using a vacuum process, photolithography, or the like.
摘要翻译：一种制造柔性半导体器件的方法包括：（i）在树脂膜的上表面上形成绝缘膜，（ii）在树脂膜的上表面上形成提取电极的图案，（iii）形成半导体层以使得半导体层与提取电极的图案接触的方式在绝缘膜上，以及（iv）在树脂膜的上表面上形成密封树脂层，使得密封树脂层覆盖半导体层和提取电极的图案，其中通过印刷方法进行上述步骤（i）至（iv）中的步骤中的至少一个。利用该制造方法，可以通过简单的印刷工艺形成各种层，而不使用真空工艺，光刻等。

6. 发明授权

US08343822B2 Flexible semiconductor device and method for manufacturing same 有权
标题翻译：柔性半导体器件及其制造方法
公开(公告)号：US08343822B2
公开(公告)日：2013-01-01
申请号：US12681445
申请日：2009-07-30
申请人： Koichi Hirano , Seiichi Nakatani , Tatsuo Ogawa , Takashi Ichiryu , Takeshi Suzuki
发明人： Koichi Hirano , Seiichi Nakatani , Tatsuo Ogawa , Takashi Ichiryu , Takeshi Suzuki
IPC分类号： H01L21/84 , H01L21/00
CPC分类号： H01L29/78651 , H01L27/1218 , H01L27/124 , H01L27/1266 , H01L29/41733 , H01L29/42384 , H01L29/78603 , H01L29/7869
摘要： A method for manufacturing a flexible semiconductor device includes (i) forming an insulating film on the upper surface of metal foil, (ii) forming an extraction electrode pattern on the upper surface of the metal foil, (iii) forming a semiconductor layer on the insulating film such that the semiconductor layer is in contact with the extraction electrode pattern, (iv) forming a sealing resin layer on the upper surface of the metal foil such that the sealing resin layer covers the semiconductor layer and the extraction electrode pattern, and (v) forming electrodes by etching the metal foil, the metal foil being used as a support for the insulating film, the extraction electrode pattern, the semiconductor layer, and the sealing resin layer formed in (i) to (iv) and used as a constituent material for the electrodes in (v). The metal foil need not be stripped, and a high-temperature process can be used.
摘要翻译：一种制造柔性半导体器件的方法包括：（i）在金属箔的上表面上形成绝缘膜，（ii）在金属箔的上表面上形成引出电极图案，（iii）在金属箔的上表面上形成半导体层绝缘膜，使得半导体层与引出电极图案接触，（iv）在金属箔的上表面上形成密封树脂层，使得密封树脂层覆盖半导体层和引出电极图案，和（ v）通过蚀刻金属箔形成电极，金属箔用作绝缘膜的支撑体，引出电极图案，半导体层和形成在（i）至（iv）中的密封树脂层，并用作（v）中的电极的构成材料。金属箔不需要剥离，可以使用高温工艺。

7. 发明授权

US08143617B2 Semiconductor device, semiconductor device manufacturing method and image display device 有权
标题翻译：半导体器件，半导体器件制造方法和图像显示器件
公开(公告)号：US08143617B2
公开(公告)日：2012-03-27
申请号：US12667297
申请日：2008-07-01
申请人： Yoshihisa Yamashita , Seiichi Nakatani
发明人： Yoshihisa Yamashita , Seiichi Nakatani
IPC分类号： H01L29/41 , H01L29/786 , H01L29/06 , H01L51/30 , H01L51/50 , H01L51/52
CPC分类号： H01L51/057 , B82Y10/00 , H01L27/3274 , H01L51/0004
摘要： A semiconductor device having semiconductor elements disposed with higher density and a method for manufacturing the same are provided. An image display device employing the semiconductor device is also provided. A semiconductor device comprises a resin film having a through hole; and a semiconductor element comprising a gate electrode disposed on the inner wall of the through hole, an insulating layer that covers the gate electrode within the through hole, an organic semiconductor disposed on the insulating layer within the through hole, and a source electrode and a drain electrode which are electrically connected to the organic semiconductor.
摘要翻译：提供了具有以更高密度设置的半导体元件的半导体器件及其制造方法。还提供了采用半导体器件的图像显示装置。半导体器件包括具有通孔的树脂膜; 以及半导体元件，包括设置在通孔的内壁上的栅电极，覆盖通孔内的栅电极的绝缘层，设置在通孔内的绝缘层上的有机半导体，以及源电极和电极与有机半导体电连接。

8. 发明授权

US08097958B2 Flip chip connection structure having powder-like conductive substance and method of producing the same 有权
标题翻译：具有粉末状导电物质的倒装芯片连接结构体及其制造方法
公开(公告)号：US08097958B2
公开(公告)日：2012-01-17
申请号：US12298464
申请日：2007-04-18
申请人： Susumu Sawada , Seiichi Nakatani , Seiji Karashima , Takashi Kitae
发明人： Susumu Sawada , Seiichi Nakatani , Seiji Karashima , Takashi Kitae
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H05K3/323 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/29 , H01L24/31 , H01L24/81 , H01L24/83 , H01L2224/13099 , H01L2224/16225 , H01L2224/16501 , H01L2224/29101 , H01L2224/29111 , H01L2224/2929 , H01L2224/293 , H01L2224/29339 , H01L2224/29347 , H01L2224/81193 , H01L2224/81801 , H01L2224/8192 , H01L2224/83192 , H01L2224/83851 , H01L2224/83855 , H01L2224/83886 , H01L2924/01005 , H01L2924/01006 , H01L2924/01009 , H01L2924/01011 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01056 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/0781 , H01L2924/14 , H01L2924/1579 , H01L2924/351 , H05K3/3436 , H05K3/3484 , H05K3/361 , H05K3/363 , H05K2203/083 , H05K2203/087 , Y02P70/613 , H01L2924/00 , H01L2924/01083 , H01L2224/29311 , H01L2924/00014 , H01L2924/00015
摘要： A connection structure (package 10) has a first plate body 101 and a second plate body; in the first plate body 101, a wiring pattern having a plurality of connection terminals 102 is formed, and the second plate body has at least two connection terminals (electrode terminals 104) arranged facing the connection terminals of the first plate body 101. The connection terminals of the first and second plate bodies are connection terminals formed as projections on the surfaces of the first and second plate bodies. A conductive substance 108 is accumulated to cover at least a part of each side face of the connection terminals opposed to each other of the first and second plate bodies, and the connection terminals thus opposed are connected to each other via the conductive substance. The package thus formed is ready for a high-pin-count, narrow-pitch configuration of a next-generation semiconductor chip, and exhibits excellent productivity and reliability. The present invention is advantageous for such a package, for a connection structure applicable to the production of the package, and for a method of producing the connection structure.
摘要翻译：连接结构（封装10）具有第一板体101和第二板体; 在第一板体101中，形成具有多个连接端子102的布线图案，第二板体具有面对第一板体101的连接端子配置的至少两个连接端子（电极端子104）。连接第一和第二板体的端子是在第一和第二板体的表面上形成为突起的连接端子。聚集导电物质108以覆盖第一和第二板体彼此相对的连接端子的每个侧面的至少一部分，并且由此相对的连接端子经由导电物质彼此连接。这样形成的封装准备好用于下一代半导体芯片的高引脚数，窄间距配置，并且表现出优异的生产率和可靠性。本发明对于这种包装，对于适用于包装的生产的连接结构以及制造连接结构的方法是有利的。

9. 发明授权

US08071425B2 Flip chip mounting body, flip chip mounting method and flip chip mounting apparatus 有权
标题翻译：倒装芯片安装体，倒装芯片安装方法和倒装芯片安装装置
公开(公告)号：US08071425B2
公开(公告)日：2011-12-06
申请号：US12764455
申请日：2010-04-21
申请人： Seiichi Nakatani , Takashi Kitae , Yoshihisa Yamashita , Takashi Ichiryu , Seiji Karashima
发明人： Seiichi Nakatani , Takashi Kitae , Yoshihisa Yamashita , Takashi Ichiryu , Seiji Karashima
IPC分类号： H01L21/52
CPC分类号： H01L24/81 , H01L21/563 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/75 , H01L24/83 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/29111 , H01L2224/2919 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/75 , H01L2224/75251 , H01L2224/83007 , H01L2224/83097 , H01L2224/83192 , H01L2224/83815 , H01L2224/83874 , H01L2224/8388 , H01L2224/83888 , H01L2224/9201 , H01L2924/00014 , H01L2924/01006 , H01L2924/01009 , H01L2924/01011 , H01L2924/01013 , H01L2924/01027 , H01L2924/01033 , H01L2924/0105 , H01L2924/01056 , H01L2924/01078 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/14 , H01L2924/181 , H01L2924/3025 , H01L2924/00 , H01L2924/0695 , H01L2224/05599
摘要： The flip chip mounted body of the present invention includes: a circuit board (213) having a plurality of connection terminals (211); a semiconductor chip (206) having a plurality of electrode terminals (207) that are disposed opposing the connection terminals (211); and a porous sheet (205) having a box shape that is provided on an opposite side of a formation surface of the electrode terminal (207) of the semiconductor chip (206), is folded on an outer periphery of the semiconductor chip (206) on the formation surface side of the electrode terminal (207) and is in contact with the circuit board (213), wherein the connection terminal (211) of the circuit board (213) and the electrode terminal (207) of the semiconductor chip (206) are connected electrically via a solder layer (215), and the circuit board (213) and the semiconductor chip (206) are fixed by a resin (217). Thereby, the flip chip mounted body with excellent productivity and reliability that can mount the semiconductor chip on the circuit board, and a method and an apparatus for mounting the flip chip mounted body are provided.
摘要翻译：本发明的倒装芯片安装体包括：具有多个连接端子（211）的电路板（213）; 具有与所述连接端子相对设置的多个电极端子（207）的半导体芯片（206）。在所述半导体芯片（206）的外周折叠具有设置在所述半导体芯片（206）的所述电极端子（207）的形成面的相反侧的盒状的多孔片（205）在电极端子（207）的形成面侧与电路基板（213）接触，电路基板（213）的连接端子（211）和半导体芯片的电极端子（207） 206）通过焊料层（215）电连接，并且电路板（213）和半导体芯片（206）由树脂（217）固定。因此，提供了将半导体芯片安装在电路板上的优异的生产率和可靠性的倒装芯片安装体以及安装倒装芯片安装体的方法和装置。

10. 发明授权

US08064213B2 Module with a built-in component, and electronic device with the same 有权
标题翻译：模块具有内置组件，电子设备具有相同的功能
公开(公告)号：US08064213B2
公开(公告)日：2011-11-22
申请号：US11043123
申请日：2005-01-27
申请人： Toshiyuki Asahi , Seiji Karashima , Takashi Ichiryu , Seiichi Nakatani , Tousaku Nishiyama
发明人： Toshiyuki Asahi , Seiji Karashima , Takashi Ichiryu , Seiichi Nakatani , Tousaku Nishiyama
IPC分类号： H05K1/18
CPC分类号： H01L21/568 , H01L21/6835 , H01L23/49805 , H01L23/5389 , H01L24/48 , H01L25/03 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L25/165 , H01L25/50 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2225/0651 , H01L2225/06524 , H01L2225/06555 , H01L2225/06582 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2225/107 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/09701 , H01L2924/12042 , H01L2924/16152 , H01L2924/181 , H01L2924/1815 , H01L2924/19105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H05K1/0284 , H05K1/183 , H05K1/187 , H05K3/20 , H05K3/403 , H05K2203/302 , H01L2924/00 , H01L2924/00012 , H01L2224/05599 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A module with a built-in component is provided which can be produced without a via-forming step. The module with a built-in component 100 includes an insulating sheet substrate 10 which has an upper surface 10a, a lower surface 10b opposed to the upper surface 10b and a side surface 10c which connects these surfaces. At least one wiring 20 extends from the upper surface to the lower surface through the side surface, and an electronic component 32 is disposed within the sheet substrate.
摘要翻译：提供具有内置部件的模块，其可以在没有通孔形成步骤的情况下制造。具有内置部件100的模块包括绝缘片基板10，其具有上表面10a，与上表面10b相对的下表面10b和连接这些表面的侧表面10c。至少一个布线20通过侧面从上表面延伸到下表面，并且电子部件32设置在片状基板内。

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