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1. 发明授权

US08340939B2 Method and apparatus for selecting paths for use in at-speed testing 有权
标题翻译：用于选择在速度测试中使用的路径的方法和装置
公开(公告)号：US08340939B2
公开(公告)日：2012-12-25
申请号：US12610090
申请日：2009-10-30
申请人： Yiyu Shi , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
发明人： Yiyu Shi , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
IPC分类号： G01R31/00
CPC分类号： G01R31/31835
摘要： In one embodiment, the invention is a method and apparatus for selecting paths for use in at-speed testing. One embodiment of a method for selecting a set of n paths with which to test an integrated circuit chip includes: organizing the set of n paths into a plurality of sub-sets, receiving a new candidate path, and adding the new candidate path to one of the sub-sets when the new candidate path improves the process coverage metric of the sub-sets.
摘要翻译：在一个实施例中，本发明是用于选择在速度测试中使用的路径的方法和装置。用于选择用于测试集成电路芯片的n个路径的集合的方法的一个实施例包括：将n个路径的集合组织成多个子集，接收新的候选路径，并将新的候选路径添加到一个当新的候选路径改进子集的过程覆盖度量时，子集的子集。

2. 发明授权

US07971120B2 Method and apparatus for covering a multilayer process space during at-speed testing 有权
标题翻译：在高速测试期间覆盖多层工艺空间的方法和装置
公开(公告)号：US07971120B2
公开(公告)日：2011-06-28
申请号：US12340072
申请日：2008-12-19
申请人： Yiyu Shi , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
发明人： Yiyu Shi , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
IPC分类号： G06F11/00
CPC分类号： G01R31/2882
摘要： In one embodiment, the invention is a method and apparatus covering a multilayer process space during at-speed testing. One embodiment of a method for selecting a set of paths with which to test a process space includes determining a number N of paths to be included in the set of paths such that at least number M of paths in N for which testing of the process space will fail, computing a metric that substantially ensures that the set of paths satisfies the requirements of N and M, and outputting the metric for use in selecting the set of paths.
摘要翻译：在一个实施例中，本发明是在高速测试期间覆盖多层工艺空间的方法和装置。用于选择用于测试处理空间的一组路径的方法的一个实施例包括确定要包括在路径集合中的路径数量N，使得至少数目M的路径在其中用于对进程空间进行测试将会失败，计算基本上确保路径组满足N和M的要求并输出用于选择路径集合的度量的度量。

3. 发明申请

US20100162064A1 METHOD AND APPARATUS FOR COVERING A MULTILAYER PROCESS SPACE DURING AT-SPEED TESTING 有权
标题翻译：用于在速度测试期间覆盖多层过程空间的方法和装置
公开(公告)号：US20100162064A1
公开(公告)日：2010-06-24
申请号：US12340072
申请日：2008-12-19
申请人： Yiyu Shi , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
发明人： Yiyu Shi , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/2882
摘要： In one embodiment, the invention is a method and apparatus covering a multilayer process space during at-speed testing. One embodiment of a method for selecting a set of paths with which to test a process space includes determining a number N of paths to be included in the set of paths such that at least number M of paths in N for which testing of the process space will fail, computing a metric that substantially ensures that the set of paths satisfies the requirements of N and M, and outputting the metric for use in selecting the set of paths.
摘要翻译：在一个实施例中，本发明是在高速测试期间覆盖多层工艺空间的方法和装置。用于选择用于测试处理空间的一组路径的方法的一个实施例包括确定要包括在路径集合中的路径数量N，使得至少数目M的路径在其中用于对进程空间进行测试将会失败，计算基本上确保路径组满足N和M要求并输出用于选择路径集合的度量的度量。

4. 发明授权

US09177940B2 Fault-tolerant unit and method for through-silicon via 有权
标题翻译：容错单元和穿硅通孔的方法
公开(公告)号：US09177940B2
公开(公告)日：2015-11-03
申请号：US13236661
申请日：2011-09-20
申请人： Chiao-Ling Lung , Yu-Shih Su , Shih-Chieh Chang , Yiyu Shi
发明人： Chiao-Ling Lung , Yu-Shih Su , Shih-Chieh Chang , Yiyu Shi
IPC分类号： H03K19/00 , H01L25/065 , H01L25/00 , H01L23/48
CPC分类号： H01L25/0657 , H01L23/481 , H01L2224/16146 , H01L2225/06544
摘要： A fault-tolerant unit and a fault-tolerant method for through-silicon via (TSV) are provided. The fault-tolerant unit includes TSV structures TSV1˜TSVn, nodes N11˜N1n, nodes N21˜N2n and a switching module. The TSV structure TSVi is connected between the node N1i of the first chip and the node N2i of the second chip, wherein 1≦i≦n. The switching module is connected between the nodes N21˜N2n of the second chip and a test path of the second chip. In normal operation state, the switching module disconnects the test path and the nodes N21˜N2n when the TSV structures TSV1˜TSVn are valid. The switching module connects the node N2i to at least another one of the nodes N21˜N2n when the TSV structure TSVi is faulty in the normal operation state. In test status, the switching module connects the test path to the nodes N21˜N2n.
摘要翻译：提供了一种容错单元和通过硅通孔（TSV）的容错方法。容错单元包括TSV结构TSV1〜TSVn，节点N11〜N1n，节点N21〜Nn以及交换模块。 TSV结构TSVi连接在第一芯片的节点N1i和第二芯片的节点N2i之间，其中1＆nlE; i＆nlE; n。切换模块连接在第二芯片的节点N21〜Nn2和第二芯片的测试路径之间。在正常工作状态下，当TSV结构TSV1〜TSVn有效时，切换模块断开测试路径和节点N21〜N2。当TSV结构TSVi在正常操作状态下故障时，切换模块将节点N2i连接到节点N21〜Nnn中的至少另一个。在测试状态下，交换模块将测试路径连接到节点N21〜N2n。

5. 发明申请

US20120248438A1 FAULT-TOLERANT UNIT AND METHOD FOR THROUGH-SILICON VIA 有权
标题翻译：耐腐蚀单元和通过硅的方法
公开(公告)号：US20120248438A1
公开(公告)日：2012-10-04
申请号：US13236661
申请日：2011-09-20
申请人： Chiao-Ling Lung , Yu-Shih Su , Shih-Chieh Chang , Yiyu Shi
发明人： Chiao-Ling Lung , Yu-Shih Su , Shih-Chieh Chang , Yiyu Shi
IPC分类号： H01L23/58 , H01L21/66
CPC分类号： H01L25/0657 , H01L23/481 , H01L2224/16146 , H01L2225/06544
摘要： A fault-tolerant unit and a fault-tolerant method for through-silicon via (TSV) are provided. The fault-tolerant unit includes TSV structures TSV1˜TSVn, nodes N11˜N1n, nodes N21˜N2n and a switching module. The TSV structure TSVi is connected between the node N11 of the first chip and the node N2i of the second chip, wherein 1≦i≦n. The switching module is connected between the nodes N21˜N2n of the second chip and a test path of the second chip. In normal operation state, the switching module disconnects the test path and the nodes N21˜N2n when the TSV structures TSV1˜TSVn are valid. The switching module connects the node N2i to at least another one of the nodes N21˜N2n when the TSV structure TSVi is faulty in the normal operation state. In test status, the switching module connects the test path to the nodes N21˜N2n.
摘要翻译：提供了一种容错单元和通过硅通孔（TSV）的容错方法。容错单元包括TSV结构TSV1〜TSVn，节点N11〜N1n，节点N21〜Nn以及交换模块。 TSV结构TSVi连接在第一芯片的节点N11和第二芯片的节点N2i之间，其中1＆nlE; i＆nlE; n。切换模块连接在第二芯片的节点N21〜Nn2和第二芯片的测试路径之间。在正常工作状态下，当TSV结构TSV1〜TSVn有效时，切换模块断开测试路径和节点N21〜N2。当TSV结构TSVi在正常操作状态下故障时，切换模块将节点N2i连接到节点N21〜Nnn中的至少另一个。在测试状态下，交换模块将测试路径连接到节点N21〜N2n。

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