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1. 发明授权

US6099662A Process for cleaning a semiconductor substrate after chemical-mechanical polishing 有权
标题翻译：化学机械抛光后清洗半导体衬底的工艺
公开(公告)号：US6099662A
公开(公告)日：2000-08-08
申请号：US248726
申请日：1999-02-11
申请人： Ying-Lang Wang , Jowei Dun , Ken-Shen Chou , Yu-Ku Lin
发明人： Ying-Lang Wang , Jowei Dun , Ken-Shen Chou , Yu-Ku Lin
IPC分类号： H01L21/02 , H01L21/306 , H01L21/3105 , H01L21/321 , B08B3/00 , H01L21/00
CPC分类号： H01L21/02065 , H01L21/02074 , H01L21/31053 , H01L21/3212
摘要： An improved method for removing residual slurry particles and metallic residues from the surface of a semiconductor substrate after chemical-mechanical polishing has been developed. The cleaning method involves sequential spray cleaning solutions of NH.sub.4 OH and H.sub.2 O, NH.sub.4 OH, H.sub.2 O.sub.2 and H.sub.2 O, HF and H.sub.2 O, and HCl, H.sub.2 O.sub.2 and H.sub.2 O. The cleaning sequence is: 1. A pre-soak in a spray solution of NH.sub.4 OH and H.sub.2 O; 2. Spray cleaning in a solution of NH.sub.4 OH, H.sub.2 O.sub.2 and H.sub.2 O; 3. Spray cleaning in a dilute solution of HF and H.sub.2 O; 4. Spray rinsing in DI-water. It is important that slurry particulates first be removed by NH.sub.4 OH, H.sub.2 O.sub.2 and H.sub.2 O, followed by spray cleaning in a dilute solution of HF and H.sub.2 O to remove metallic residues. The spray cleaning method is superior to brush cleaning methods for both oxide-CMP and tungsten-CMP and results in superior removal of slurry particles and metallic residues introduced by the CMP processes. An optional spray cleaning step using a solution of HCl, H.sub.2 O.sub.2 and H.sub.2 O results in further reduction of metallic residue contamination following oxide-CMP. Compared to traditional brush cleaning the new spray cleaning process has a 2.times. improvement in throughput, less consumption of DI water, and low risk of cross-contamination between sequentially cleaned substrates.
摘要翻译：已经开发了用于在化学机械抛光之后从半导体衬底的表面除去残余浆料颗粒和金属残留物的改进方法。清洗方法包括NH 4 OH和H 2 O，NH 4 OH，H 2 O 2和H 2 O，HF和H 2 O以及HCl，H 2 O 2和H 2 O的顺序喷雾清洗溶液。清洗顺序为：1.在NH4OH和H2O的喷雾溶液中预浸泡; 2.在NH4OH，H2O2和H2O溶液中喷雾清洗; 3.在HF和H2O的稀溶液中喷雾清洗; 4.在DI水中喷淋。重要的是，首先通过NH 4 OH，H 2 O 2和H 2 O除去浆料颗粒，然后在HF和H 2 O的稀溶液中喷雾清洗以除去金属残余物。喷雾清洗方法优于氧化物CMP和钨-CMP两者的刷子清洗方法，并且优异地除去由CMP工艺引入的浆料颗粒和金属残留物。使用HCl，H2O2和H2O溶液的可选喷雾清洗步骤可以进一步降低氧化物CMP后的金属残留污染。与传统的刷子清洁相比，新的喷雾清洁过程在吞吐量方面有2倍的改善，更少的去离子水消耗，以及顺序清洗的基材之间交叉污染的风险较低。

2. 发明授权

US06395635B1 Reduction of tungsten damascene residue 有权
标题翻译：还原钨镶嵌残渣
公开(公告)号：US06395635B1
公开(公告)日：2002-05-28
申请号：US09206741
申请日：1998-12-07
申请人： Ying-Lang Wang , Jowei Dun
发明人： Ying-Lang Wang , Jowei Dun
IPC分类号： H01L21302
CPC分类号： H01L21/31053 , H01L21/3212
摘要： A CMP process is provided for the reduction of tungsten damascene residue and the elimination of surface scratch within the surface that is being polished. A three step polishing procedure of the ILD is followed by a two step buffing procedure of the ILD. The three step polishing procedure reduces the device defect count by eliminating damascene residue from the polished surface. The two step buffing procedure reduces micro scratch within the polished surface thus improving device throughput. A two step buffing procedure is applied to the IMD. Oxide buffing is applied and consists of a three step polishing procedure followed by a two step buffing procedure.
摘要翻译：提供了一种CMP工艺，用于减少钨镶嵌残余物并消除正在抛光的表面内的表面划痕。 ILD的三步抛光程序之后是ILD的两步抛光程序。三步抛光程序通过从抛光表面去除镶嵌残留物来减少设备缺陷计数。两步抛光程序减少抛光表面内的微刮痕，从而提高设备的生产能力。对IMD应用两步抛光程序。应用氧化物抛光，并由三步抛光程序组成，其后是两步抛光程序。

3. 发明授权

US06281146B1 Plasma enhanced chemical vapor deposition (PECVD) method for forming microelectronic layer with enhanced film thickness uniformity 有权
标题翻译：用于形成具有增强的膜厚度均匀性的微电子层的等离子体增强化学气相沉积（PECVD）方法
公开(公告)号：US06281146B1
公开(公告)日：2001-08-28
申请号：US09396517
申请日：1999-09-15
申请人： Ying-Lang Wang , Hui-Ling Wang , Jowei Dun , Szu-An Wu
发明人： Ying-Lang Wang , Hui-Ling Wang , Jowei Dun , Szu-An Wu
IPC分类号： H01L2131
CPC分类号： H01L21/02164 , C23C16/402 , C23C16/5096 , H01L21/02211 , H01L21/02274 , H01L21/31612
摘要： A method for forming a microelectronic layer. There is first provided a substrate. There is then formed over the substrate the microelectronic layer while employing a plasma enhanced chemical vapor deposition (PECVD) method employing a source material gas and a carrier gas, wherein there is employed a sufficiently low plasma power, a sufficiently low source material gas:carrier gas flow rate ratio and a sufficiently high carrier gas atomic mass such that the microelectronic layer is formed with enhanced film thickness uniformity. The method may be employed for forming ion implant screen layers, such as silicon oxide ion implant screen layers, with enhanced film thickness uniformity.
摘要翻译：一种形成微电子层的方法。首先提供基板。然后在采用使用源材料气体和载气的等离子体增强化学气相沉积（PECVD）方法的基板上形成微电子层，其中采用足够低的等离子体功率，足够低的源材料气体：载体气体流量比和足够高的载气原子质量，使得微电子层形成为具有增强的膜厚均匀性。该方法可用于形成具有增强的膜厚度均匀性的离子注入屏幕层，例如氧化硅离子注入屏幕层。

4. 发明授权

US06479881B2 Low temperature process for forming intermetal gap-filling insulating layers in silicon wafer integrated circuitry 有权
标题翻译：在硅晶片集成电路中形成金属间隙填充绝缘层的低温工艺
公开(公告)号：US06479881B2
公开(公告)日：2002-11-12
申请号：US09882678
申请日：2001-06-18
申请人： Ying-Lang Wang , Chun-Ching Tsan , Jowei Dun , Hung-Ju Chien
发明人： Ying-Lang Wang , Chun-Ching Tsan , Jowei Dun , Hung-Ju Chien
IPC分类号： H01L2900
CPC分类号： H01L21/76801 , H01L21/31612 , H01L21/76837 , Y10S438/937
摘要： A semiconductor wafer having a double inter-metal dielectric layer formed in the gaps of and on closely. spaced metal interconnection circuitry. The double dielectric layer is formed by an in situ low temperature two step deposition HDP-CVD process separated by a cool-down period. The low temperature process mitigates metal line defects such as distortion or warping caused by heat generated during the process of filling gaps having aspect ratios greater than 2. The double dielectric layer is composed of Group IV materials, silicon being the preferred material. These double layers may be individually doped. Titanium nitride layers, present as by-products of seeding and anti-reflective coatings serve to reduce electro-migration of the metal circuitry.
摘要翻译：一种半导体晶片，其具有形成在间隙中并紧密地形成的双金属介电层。间隔金属互连电路。双电介质层通过在冷却期间分离的原位低温两步沉积HDP-CVD工艺形成。低温处理减轻了金属线缺陷，例如在填充具有大于2的纵横比的间隙的过程中产生的热引起的变形或翘曲。双电介质层由第IV族材料组成，硅是优选的材料。这些双层可以单独掺杂。作为接种和抗反射涂层的副产物存在的氮化钛层用于减少金属电路的电迁移。

5. 发明授权

US06291872B1 Three-dimensional type inductor for mixed mode radio frequency device 有权
标题翻译：用于混合模式射频设备的三维型电感器
公开(公告)号：US06291872B1
公开(公告)日：2001-09-18
申请号：US09433255
申请日：1999-11-04
申请人： Ying-Lang Wang , Hway-Chi Lin , Jun Wu , Jowei Dun
发明人： Ying-Lang Wang , Hway-Chi Lin , Jun Wu , Jowei Dun
IPC分类号： H01L2900
CPC分类号： H01L28/10 , H01F17/0013 , H01L27/08
摘要： Vertical type structures for integrated circuit inductors are disclosed. These vertical type inductors include the single-loop type, the parallel-loop type and the screw type, which form three different embodiments in the present invention. In the first embodiment, three-dimensional type structures, a single-loop type is utilized as an integrated circuit inductor. This inductor structure is formed on a substrate and the axis of the structure is upright to the substrate. In another embodiment according to the present invention, a parallel-loop type structure for radio frequency (RF) integrated circuit inductor is provided. A screw type structure according to this invention is the third embodiment. It features an axis that is parallel to the surface of the substrate and threads into the semiconductor device.
摘要翻译：公开了集成电路电感器的垂直型结构。这些垂直型电感器包括在本发明中形成三个不同实施例的单环型，并联环型和螺旋型。在第一实施例中，采用单环型的三维型结构作为集成电路电感器。该电感器结构形成在基板上，并且该结构的轴线垂直于基板。在根据本发明的另一实施例中，提供了一种用于射频（RF）集成电路电感器的并联环路结构。根据本发明的螺杆型结构是第三实施例。它具有平行于衬底表面并进入半导体器件的轴线。

6. 发明授权

US06268274B1 Low temperature process for forming inter-metal gap-filling insulating layers in silicon wafer integrated circuitry 有权
标题翻译：用于在硅晶片集成电路中形成金属间间隙填充绝缘层的低温工艺
公开(公告)号：US06268274B1
公开(公告)日：2001-07-31
申请号：US09418032
申请日：1999-10-14
申请人： Ying-Lang Wang , Chun-Ching Tsan , Jowei Dun , Hung-Ju Chien
发明人： Ying-Lang Wang , Chun-Ching Tsan , Jowei Dun , Hung-Ju Chien
IPC分类号： H01L2100
CPC分类号： H01L21/76801 , H01L21/31612 , H01L21/76837 , Y10S438/937
摘要： This invention provides an in situ low temperature, two step deposition HDP-CVD process separated by a cooldown period, for forming an inter-metal dielectric passivation layer for an integrated circuit structure. Said process mitigating metal line defects such as distortion or warping caused by excessive heat generated during the etching/deposition process.
摘要翻译：本发明提供了一种在冷却期间分离的原位低温两步沉积HDP-CVD工艺，用于形成用于集成电路结构的金属间介电钝化层。所述方法减轻金属线缺陷，例如在蚀刻/沉积工艺期间产生的过多热引起的变形或翘曲。

7. 发明授权

US06291331B1 Re-deposition high compressive stress PECVD oxide film after IMD CMP process to solve more than 5 metal stack via process IMD crack issue 有权
标题翻译：重新沉积高压应力PECVD氧化膜经IMD CMP工艺解决超过5个金属堆叠通过工艺IMD裂纹问题
公开(公告)号：US06291331B1
公开(公告)日：2001-09-18
申请号：US09412654
申请日：1999-10-04
申请人： Ying-Lang Wang , Jowei Dun , Ming-Jer Lee , Tong-Hua Kuan
发明人： Ying-Lang Wang , Jowei Dun , Ming-Jer Lee , Tong-Hua Kuan
IPC分类号： H01L2144
CPC分类号： H01L21/76801 , H01L2224/02166 , H01L2224/05093
摘要： A new method is provided for the creation of layers of dielectric that are used for metal stack interconnect layers where the metal stack exceeds five layers. A stack of five layers of metal interconnect lines contains one layer of Intra Metal dielectric (ILD) and four layers of Inter Metal dielectric (IMD). One or more of the layers of IMD can be formed in the conventional method. One or more of the layers of IMD can be formed in the conventional method after which a layer of high compressive PECVD is deposited over this one or more layers of IMD. The layer of high compressive PECVD provides a crack resistant film that eliminates the formation of cracks in the surface of the IMD.
摘要翻译：提供了一种新的方法，用于创建用于金属堆叠互连层的电介质层，其中金属叠层超过五层。五层金属互连线的堆叠包含一层金属介电介质（ILD）和四层金属间介质（IMD）。 IMD的一个或多个层可以用常规方法形成。可以以常规方法形成IMD的一个或多个层，之后在该一个或多个IMD层上沉积高压缩PECVD层。高压缩PECVD层提供了抗裂膜，消除了在IMD表面形成裂缝。

8. 发明授权

US09419155B2 Sensing product and method of making 有权
标题翻译：感知产品和制作方法
公开(公告)号：US09419155B2
公开(公告)日：2016-08-16
申请号：US13343922
申请日：2012-01-05
申请人： Shih-Chieh Chang , Yu-Ku Lin , Ying-Lang Wang
发明人： Shih-Chieh Chang , Yu-Ku Lin , Ying-Lang Wang
IPC分类号： H01L31/0232 , H01L31/101 , H01L31/18
CPC分类号： H01L31/0232 , H01L31/02327 , H01L31/101 , H01L31/18
摘要： This description relates to a sensing product formed using a substrate with a plurality of epi-layers. At least a first epi-layer has a different composition than the composition of a second epi-layer. The sensing product optionally includes at least one radiation sensing element in the second epi-layer and optionally an interconnect structure over the second epi-layer. The sensing product is formed by removing the substrate and all epi-layers other than the second epi-layer. A light incident surface of the second epi-layer has a total thickness variation of less than about 0.15 μm.
摘要翻译：该描述涉及使用具有多个外延层的基板形成的感测产品。至少第一外延层具有与第二外延层的组成不同的组成。感测产品可选地包括第二外延层中的至少一个辐射感测元件以及可选地在第二外延层上的互连结构。通过去除衬底和除第二外延层之外的所有外延层形成传感产物。第二外延层的光入射表面具有小于约0.15μm的总厚度变化。

9. 发明授权

US07312149B2 Copper plating of semiconductor devices using single intermediate low power immersion step 有权
标题翻译：采用单中级低功耗浸入式半导体器件镀铜
公开(公告)号：US07312149B2
公开(公告)日：2007-12-25
申请号：US10840095
申请日：2004-05-06
申请人： Chao-Lung Chen , Kei-Wei Chen , Shih-Ho Lin , Ying-Lang Wang , Yu-Ku Lin , Ching-Hwanq Su , Po-Jen Shih , Shang-Chin Sung
发明人： Chao-Lung Chen , Kei-Wei Chen , Shih-Ho Lin , Ying-Lang Wang , Yu-Ku Lin , Ching-Hwanq Su , Po-Jen Shih , Shang-Chin Sung
IPC分类号： H01L21/44
CPC分类号： C25D7/123 , C25D3/02 , C25D5/10 , C25D5/18 , H01L21/2885
摘要： A method of electroplating a metal layer on a semiconductor device includes a sequence of biasing operations that includes a first electroplating step at a first current density followed by a second immersion step at a second current density being less than the first current density, and subsequent electroplating steps of increasing current densities beginning with a third electroplating step having a third current density that is greater than the first current density. The second, low current density immersion step improves the quality of the plating process and produces a plated film that completely fills openings such as vias and trenches and avoids hollow vias and pull-back on the bottom corners of via and trench openings. The low current density second immersion step produces an electrochemical deposition process that provides low contact resistance and therefore reduces device failure.
摘要翻译：在半导体器件上电镀金属层的方法包括一系列偏置操作，其包括第一电流密度的第一电镀步骤，随后是第二电流密度小于第一电流密度的第二浸入步骤，随后的电镀从具有大于第一电流密度的第三电流密度的第三电镀步骤开始增加电流密度的步骤。第二，低电流密度浸没步骤提高了电镀工艺的质量，并且产生完全填充诸如通孔和沟槽等开口的电镀膜，并避免了通孔和沟槽开口的底角上的中空通孔和拉回。低电流密度第二浸入步骤产生电化学沉积工艺，其提供低接触电阻并因此减少器件故障。

10. 发明授权

US06863491B2 Catch-pin water support for process chamber 失效
标题翻译：捕捉针水处理室支撑
公开(公告)号：US06863491B2
公开(公告)日：2005-03-08
申请号：US10339691
申请日：2003-01-08
申请人： Hsi-Kuei Cheng , Chun-Tse Lin , Ting-Chun Wang , Yu-Ku Lin , Ying-Lang Wang
发明人： Hsi-Kuei Cheng , Chun-Tse Lin , Ting-Chun Wang , Yu-Ku Lin , Ying-Lang Wang
IPC分类号： H01L21/687 , B23B31/16
CPC分类号： H01L21/68707 , Y10T279/1033 , Y10T279/1291 , Y10T279/19
摘要： A new and improved wafer support for supporting wafers in a process chamber such as an edge bead removal (EBR) chamber. The wafer support comprises multiple wafer support units each including a gripper block that engages an edge portion or bevel of the wafer. The gripper block is attached to an engaging and disengaging mechanism for selectively causing engagement of the gripper blocks with the wafer to support the wafer and disengagement of the gripper blocks from the wafer to release the wafer for removal of the wafer from the chamber. The gripper blocks contact little or none of the surface area on the patterned surface of the wafer to prevent or substantially reduce the formation of contact-induced defects on the wafer.
摘要翻译：一种新的和改进的晶片支撑件，用于在诸如边缘珠去除（EBR）室的处理室中支撑晶片。晶片支撑件包括多个晶片支撑单元，每个晶片支撑单元包括接合晶片的边缘部分或斜面的夹持块。夹持块附接到接合和分离机构，用于选择性地使夹持器块与晶片接合以支撑晶片，并且将夹持器块与晶片分离，以释放晶片以从晶片移除。夹持器块几乎不接触晶片的图案化表面上的表面积，以防止或基本上减少晶片上接触引起的缺陷的形成。

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