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1. 发明授权

US07501149B2 Electrode and method for forming the same 有权
标题翻译：电极及其形成方法
公开(公告)号：US07501149B2
公开(公告)日：2009-03-10
申请号：US11324630
申请日：2006-01-04
申请人： Ying-Chiang Hu , Yii-Tay Chiou , Chun-Hsun Chu , Bor-Chen Tsai
发明人： Ying-Chiang Hu , Yii-Tay Chiou , Chun-Hsun Chu , Bor-Chen Tsai
IPC分类号： B05D5/12 , B05D3/00
CPC分类号： H05K3/102 , H01L2924/0002 , H05K3/1216 , H05K3/1241 , H05K3/38 , H05K2203/0783 , H05K2203/121 , Y10T29/49204 , H01L2924/00
摘要： An electrode and a method for forming the electrode. The electrode comprises: a substrate; and a plurality of metal particles adhering to the substrate. The method comprises steps of: providing a substrate; providing a solution including a solvent and a plurality of metal particles on the substrate; removing the solvent; and making the plurality of metal particles adhere to the substrate.
摘要翻译：电极和形成电极的方法。电极包括：基底; 以及附着在基板上的多个金属粒子。该方法包括以下步骤：提供衬底; 在基板上提供包括溶剂和多个金属颗粒的溶液; 除去溶剂; 并使多个金属颗粒附着在基板上。

2. 发明申请

US20070080462A1 Electrode and method for forming the same 有权
标题翻译：电极及其形成方法
公开(公告)号：US20070080462A1
公开(公告)日：2007-04-12
申请号：US11324630
申请日：2006-01-04
申请人： Ying-Chiang Hu , Yii-Tay Chiou , Chun-Hsun Chu , Bor-Chen Tsai
发明人： Ying-Chiang Hu , Yii-Tay Chiou , Chun-Hsun Chu , Bor-Chen Tsai
IPC分类号： H01L23/48
CPC分类号： H05K3/102 , H01L2924/0002 , H05K3/1216 , H05K3/1241 , H05K3/38 , H05K2203/0783 , H05K2203/121 , Y10T29/49204 , H01L2924/00
摘要： An electrode and a method for forming the electrode. The electrode comprises: a substrate; and a plurality of metal particles adhering to the substrate. The method comprises steps of: providing a substrate; providing a solution including a solvent and a plurality of metal particles on the substrate; removing the solvent; and making the plurality of metal particles adhere to the substrate.
摘要翻译：电极和形成电极的方法。电极包括：基底; 以及附着在基板上的多个金属粒子。该方法包括以下步骤：提供衬底; 在基板上提供包括溶剂和多个金属颗粒的溶液; 除去溶剂; 并使多个金属颗粒附着在基板上。

3. 发明授权

US07198413B2 Parallel optical subassembly module structure 有权
标题翻译：平行光学组件模块结构
公开(公告)号：US07198413B2
公开(公告)日：2007-04-03
申请号：US10915369
申请日：2004-08-11
申请人： Chih-Ting Kao , Chih-Hsiang Ko , Bor-Chen Tsai , Chun-Hsun Chu , Yii-Tay Chiou , Jung-Tai Chen
发明人： Chih-Ting Kao , Chih-Hsiang Ko , Bor-Chen Tsai , Chun-Hsun Chu , Yii-Tay Chiou , Jung-Tai Chen
IPC分类号： G02B6/36
CPC分类号： G02B6/4249 , G02B6/4214 , G02B6/4292
摘要： A parallel optical subassembly module structure comprises an opto-electronic device array, a base with a reflecting slope, and a micro-lens array plate with an inclined plane provided with a specific angle. The optical signal emitted from the opto-electronic device array reflects by the reflecting slope and is incident into the inclined plane of the micro-lens array plate with the specific angle. The inclined plane rectifies the optical signal to output in horizontal direction. Then the optical signal couples with the external fibers through each micro lens of the micro-lens array. The pathway of receiving the optical signal is the same as described above, but in reverse direction.
摘要翻译：平行光学子组件模块结构包括光电子器件阵列，具有反射斜面的基底和具有设置有特定角度的倾斜平面的微透镜阵列板。从光电子器件阵列发射的光信号由反射斜面反射并以特定角度入射到微透镜阵列板的倾斜平面中。倾斜平面将光信号整流以在水平方向上输出。然后，光信号通过微透镜阵列的每个微透镜与外部光纤耦合。接收光信号的路径与上述相同，但是相反。

4. 发明申请

US20050185896A1 Parallel optical subassembly module structure 有权
标题翻译：平行光学组件模块结构
公开(公告)号：US20050185896A1
公开(公告)日：2005-08-25
申请号：US10915369
申请日：2004-08-11
申请人： Chih-Ting Kao , Chih-Hsiang Ko , Bor-Chen Tsai , Chun-Hsun Chu , Yii-Tay Chiou , Jung-Tai Chen
发明人： Chih-Ting Kao , Chih-Hsiang Ko , Bor-Chen Tsai , Chun-Hsun Chu , Yii-Tay Chiou , Jung-Tai Chen
IPC分类号： G02B6/00 , G02B6/36 , G02B6/42 , H04B10/00
CPC分类号： G02B6/4249 , G02B6/4214 , G02B6/4292
摘要： A parallel optical subassembly module structure comprises an opto-electronic device array, a base with a reflecting slope, and a micro-lens array plate with an inclined plane provided with a specific angle. The optical signal emitted from the opto-electronic device array reflects by the reflecting slope and is incident into the inclined plane of the micro-lens array plate with the specific angle. The inclined plane rectifies the optical signal to output in horizontal direction. Then the optical signal couples with the external fibers through each micro lens of the micro-lens array. The pathway of receiving the optical signal is the same as described above, but in reverse direction.
摘要翻译：平行光学子组件模块结构包括光电子器件阵列，具有反射斜面的基底和具有设置有特定角度的倾斜平面的微透镜阵列板。从光电子器件阵列发射的光信号由反射斜面反射并以特定角度入射到微透镜阵列板的倾斜平面中。倾斜平面将光信号整流以在水平方向上输出。然后，光信号通过微透镜阵列的每个微透镜与外部光纤耦合。接收光信号的路径与上述相同，但是相反。

5. 发明申请

US20060110106A1 Fiber waveguide optical subassembly module 有权
标题翻译：光纤波导光学组件模块
公开(公告)号：US20060110106A1
公开(公告)日：2006-05-25
申请号：US11105514
申请日：2005-04-14
申请人： Ming-Lang Tsai , Ming-Jie Chou , Bor-Chen Tsai , Zong-Yuan Wu , Chih-Hsiang Ko , Chin-Sheng Chang , Yii-Tay Chiou , Chun-Hsun Chu , Jung-Tai Chen
发明人： Ming-Lang Tsai , Ming-Jie Chou , Bor-Chen Tsai , Zong-Yuan Wu , Chih-Hsiang Ko , Chin-Sheng Chang , Yii-Tay Chiou , Chun-Hsun Chu , Jung-Tai Chen
IPC分类号： G02B6/36
CPC分类号： G02B6/4246
摘要： A fiber waveguide optical subassembly uses the multi-mode fiber to increase the alignment tolerance between the active optical element and the waveguide. The filter is thinner to lower the dispersion due to the optical coupling gap. The subassembly further combines the optical bench to achieve passive positioning. Therefore it reduces the cost and enhances the transmission rate.
摘要翻译：光纤波导光学子组件使用多模光纤来增加有源光学元件与波导之间的对准公差。由于光耦合间隙，滤光片较薄以降低色散。该子组件进一步组合光学台以实现被动定位。因此降低成本，提高传输速率。

6. 发明授权

US07409124B2 Fiber waveguide optical subassembly module 有权
标题翻译：光纤波导光学组件模块
公开(公告)号：US07409124B2
公开(公告)日：2008-08-05
申请号：US11105514
申请日：2005-04-14
申请人： Ming-Lang Tsai , Ming Jie Chou , Bor-Chen Tsai , Zong-Yuan Wu , Chih-Hsiang Ko , Chin-Sheng Chang , Yii-Tay Chiou , Chun-Hsun Chu , Jung-Tai Chen
发明人： Ming-Lang Tsai , Ming Jie Chou , Bor-Chen Tsai , Zong-Yuan Wu , Chih-Hsiang Ko , Chin-Sheng Chang , Yii-Tay Chiou , Chun-Hsun Chu , Jung-Tai Chen
IPC分类号： G02B6/30 , G02B6/36
CPC分类号： G02B6/4246
摘要： A fiber waveguide optical subassembly uses the multi-mode fiber to increase the alignment tolerance between the active optical element and the waveguide. The filter is thinner to lower the dispersion due to the optical coupling gap. The subassembly further combines the optical bench to achieve passive positioning. Therefore it reduces the cost and enhances the transmission rate.
摘要翻译：光纤波导光学子组件使用多模光纤来增加有源光学元件与波导之间的对准公差。由于光耦合间隙，滤光片较薄以降低色散。该子组件进一步组合光学台以实现被动定位。因此降低成本，提高传输速率。

7. 发明申请

US20060211936A1 Flexible biomonitor 审中-公开
标题翻译：灵活的生物监测器
公开(公告)号：US20060211936A1
公开(公告)日：2006-09-21
申请号：US11132216
申请日：2005-05-19
申请人： Ying-Chiang Hu , Yi-Tay Chiou , Chun-Hsun Chu , Bor-Chen Tsai
发明人： Ying-Chiang Hu , Yi-Tay Chiou , Chun-Hsun Chu , Bor-Chen Tsai
IPC分类号： A61B5/04 , A61B5/02 , A61B5/00
CPC分类号： A61B5/0002 , A61B5/01 , A61B5/02438 , A61B2560/0412
摘要： A flexible biomonitor comprises a flexible substrate, a circuit apparatus, a plurality of gauges, a RFID sensing chip, a micro-antenna, and a power supply. The flexible substrate has a plurality of through holes formed thereon. The circuit apparatus is electrically connected with the gauges via the through holes to sense and treat a physiological signal. The micro-antenna is electrically connected with the circuit apparatus to transmit this physiological signal. The power supply is designed to provide electric power. Thereupon the flexible biomonitor can be plastered on the skin where the human body needs to be monitored to achieve the purposes of reducing occupied area and providing comfortable wear. Besides, it is capable of remote real-time monitoring this signal to achieve the purpose of home care.
摘要翻译：灵活的生物体包括柔性基底，电路装置，多个量规，RFID感测芯片，微型天线和电源。柔性基板具有形成在其上的多个通孔。电路装置经由通孔与量规电连接以感测和处理生理信号。微型天线与电路装置电连接以传送该生理信号。电源设计用于提供电力。因此，柔性生物监测器可以涂抹在需要监测人体的皮肤上，以达到减少占地面积和提供舒适磨损的目的。此外，它能够远程实时监控此信号，以达到家庭护理的目的。

8. 发明申请

US20090121299A1 Wafer level sensing package and manufacturing process thereof 审中-公开
标题翻译：晶圆级感测封装及其制造工艺
公开(公告)号：US20090121299A1
公开(公告)日：2009-05-14
申请号：US12073392
申请日：2008-03-05
申请人： Lung-Tai Chen , Chun-Hsun Chu , Tzong-Che Ho , Bor-Chen Tsai
发明人： Lung-Tai Chen , Chun-Hsun Chu , Tzong-Che Ho , Bor-Chen Tsai
IPC分类号： H01L29/00 , H01L21/00
CPC分类号： B81C1/00793 , B81B7/0054 , B81B2201/0292 , B81B2207/07 , B81C1/00182 , B81C2201/053 , H01L2224/0401 , H01L2224/05548 , H01L2224/13023 , H01L2924/1461 , H01L2924/00
摘要： A wafer level sensing package and manufacturing process thereof are described. The process includes providing a wafer having sensing chips, in which each sensing chip has a sensing area and pads; forming a stress release layer on a wafer surface; cladding a photoresist layer on the stress release layer; patterning the photoresist layer to expose the pads and a portion of the stress release layer, without exposing opening areas of the sensing areas; forming a conductive metal layer of re-distributed pads on the portion of the stress release layer exposed by the photoresist layer; removing the photoresist layer; forming a re-cladding photoresist layer on the stress release layer and the conductive metal layer; forming holes in the re-cladding photoresist layer above the re-distributed pad area; and forming conductive bumps in the holes to electrically connect to the conductive metal layer.
摘要翻译：描述了晶片级感测封装及其制造工艺。该过程包括提供具有感测芯片的晶片，其中每个感测芯片具有感测区域和焊盘; 在晶片表面上形成应力释放层; 在应力释放层上包覆光致抗蚀剂层; 图案化光致抗蚀剂层以暴露垫和应力释放层的一部分，而不暴露感测区域的开口区域; 在由光致抗蚀剂层暴露的应力释放层的部分上形成再分布焊盘的导电金属层; 去除光致抗蚀剂层; 在所述应力释放层和所述导电金属层上形成再包覆光致抗蚀剂层; 在再分布的焊盘区域上方的再包层光致抗蚀剂层中形成孔; 以及在所述孔中形成导电凸块以电连接到所述导电金属层。

9. 发明授权

US07915065B2 Wafer level sensing package and manufacturing process thereof 有权
标题翻译：晶圆级感测封装及其制造工艺
公开(公告)号：US07915065B2
公开(公告)日：2011-03-29
申请号：US12331539
申请日：2008-12-10
申请人： Lung-Tai Chen , Chun-Hsun Chu , Tzong-Che Ho , Bor-Chen Tsai
发明人： Lung-Tai Chen , Chun-Hsun Chu , Tzong-Che Ho , Bor-Chen Tsai
IPC分类号： H01L21/00
CPC分类号： B81C1/00793 , B81B7/0054 , B81B2201/0292 , B81B2207/07 , B81C1/00182 , B81C2201/053 , H01L2224/0401 , H01L2224/05548 , H01L2224/13023 , H01L2924/1461 , H01L2924/00
摘要： A wafer level sensing package and manufacturing process thereof are described. The process includes providing a wafer having sensing chips, in which each sensing chip has a sensing area and pads; forming a stress release layer on a wafer surface; cladding a photoresist layer on the stress release layer; patterning the photoresist layer to expose the pads and a portion of the stress release layer, without exposing opening areas of the sensing areas; forming a conductive metal layer of re-distributed pads on the portion of the stress release layer exposed by the photoresist layer; removing the photoresist layer; forming a re-cladding photoresist layer on the stress release layer and the conductive metal layer; forming holes in the re-cladding photoresist layer above the re-distributed pad area; and forming conductive bumps in the holes to electrically connect to the conductive metal layer.
摘要翻译：描述了晶片级感测封装及其制造工艺。该过程包括提供具有感测芯片的晶片，其中每个感测芯片具有感测区域和焊盘; 在晶片表面上形成应力释放层; 在应力释放层上包覆光致抗蚀剂层; 图案化光致抗蚀剂层以暴露垫和应力释放层的一部分，而不暴露感测区域的开口区域; 在由光致抗蚀剂层暴露的应力释放层的部分上形成再分布焊盘的导电金属层; 去除光致抗蚀剂层; 在所述应力释放层和所述导电金属层上形成再包覆光致抗蚀剂层; 在再分布的焊盘区域上方的再包层光致抗蚀剂层中形成孔; 以及在所述孔中形成导电凸块以电连接到所述导电金属层。

10. 发明申请

US20090124074A1 WAFER LEVEL SENSING PACKAGE AND MANUFACTURING PROCESS THEREOF 有权
标题翻译： WAFER水平感测包装及其制造工艺
公开(公告)号：US20090124074A1
公开(公告)日：2009-05-14
申请号：US12331539
申请日：2008-12-10
申请人： Lung-Tai Chen , Chun-Hsun Chu , Tzong-Che Ho , Bor-Chen Tsai
发明人： Lung-Tai Chen , Chun-Hsun Chu , Tzong-Che Ho , Bor-Chen Tsai
IPC分类号： H01L21/768
CPC分类号： B81C1/00793 , B81B7/0054 , B81B2201/0292 , B81B2207/07 , B81C1/00182 , B81C2201/053 , H01L2224/0401 , H01L2224/05548 , H01L2224/13023 , H01L2924/1461 , H01L2924/00
摘要： A wafer level sensing package and manufacturing process thereof are described. The process includes providing a wafer having sensing chips, in which each sensing chip has a sensing area and pads; forming a stress release layer on a wafer surface; cladding a photoresist layer on the stress release layer; patterning the photoresist layer to expose the pads and a portion of the stress release layer, without exposing opening areas of the sensing areas; forming a conductive metal layer of re-distributed pads on the portion of the stress release layer exposed by the photoresist layer; removing the photoresist layer; forming a re-cladding photoresist layer on the stress release layer and the conductive metal layer; forming holes in the re-cladding photoresist layer above the re-distributed pad area; and forming conductive bumps in the holes to electrically connect to the conductive metal layer.
摘要翻译：描述了晶片级感测封装及其制造工艺。该过程包括提供具有感测芯片的晶片，其中每个感测芯片具有感测区域和焊盘; 在晶片表面上形成应力释放层; 在应力释放层上包覆光致抗蚀剂层; 图案化光致抗蚀剂层以暴露垫和应力释放层的一部分，而不暴露感测区域的开口区域; 在由光致抗蚀剂层暴露的应力释放层的部分上形成再分布焊盘的导电金属层; 去除光致抗蚀剂层; 在所述应力释放层和所述导电金属层上形成再包覆光致抗蚀剂层; 在再分布的焊盘区域上方的再包层光致抗蚀剂层中形成孔; 并且在所述孔中形成导电凸块以电连接到所述导电金属层。

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