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1. 发明授权

US08384226B2 Hybrid bump capacitor 失效
标题翻译：混合电容器
公开(公告)号：US08384226B2
公开(公告)日：2013-02-26
申请号：US12885722
申请日：2010-09-20
申请人： Yikui (Jen) Dong , Steven L. Howard , Freeman Y. Zhong , David S. Lowrie
发明人： Yikui (Jen) Dong , Steven L. Howard , Freeman Y. Zhong , David S. Lowrie
IPC分类号： H01L23/48 , H01L27/108 , H01L21/00
CPC分类号： H01G4/228 , H01G4/30 , H01L23/5223 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A device fabricated on a chip is disclosed. The device generally includes (A) a first pattern and a second pattern both created in an intermediate conductive layer of the chip, (B) at least one via created in an insulating layer above the intermediate conductive layer and (C) a first bump created in a top conductive layer above the insulating layer. The first pattern generally establishes a first of a plurality of plates of a first capacitor. The via may be aligned with the second pattern. The first bump may (i) be located directly above the first plate, (ii) establish a second of the plates of the first capacitor, (iii) be suitable for flip-chip bonding, (iv) connect to the second pattern through the via such that both of the plates of the first capacitor are accessible in the intermediate conductive layer. The first pattern and the second pattern may be shaped as interlocking combs.
摘要翻译：公开了一种在芯片上制造的器件。该装置通常包括（A）在芯片的中间导电层中产生的第一图案和第二图案，（B）在中间导电层上方的绝缘层中形成的至少一个通孔，（C）产生的第一凸起在绝缘层上方的顶部导电层中。第一图案通常建立第一电容器的多个板中的第一个。通孔可以与第二图案对准。第一凸块可以（i）位于第一板的正上方，（ii）建立第一电容器的第二板，（iii）适于倒装芯片接合，（iv）通过通过使得第一电容器的两个板可在中间导电层中接近。第一图案和第二图案可以被成形为互锁梳。

2. 发明授权

US07825522B2 Hybrid bump capacitor 有权
标题翻译：混合电容器
公开(公告)号：US07825522B2
公开(公告)日：2010-11-02
申请号：US11741195
申请日：2007-04-27
申请人： Yikui (Jen) Dong , Steven L. Howard , Freeman Y. Zhong , David S. Lowrie
发明人： Yikui (Jen) Dong , Steven L. Howard , Freeman Y. Zhong , David S. Lowrie
IPC分类号： H01L23/48 , H01L27/108
CPC分类号： H01G4/228 , H01G4/30 , H01L23/5223 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A device fabricated on a chip is disclosed. The device generally includes (A) a first pattern and a second pattern both created in an intermediate conductive layer of the chip, (B) at least one via created in an insulating layer above the intermediate conductive layer and (C) a first bump created in a top conductive layer above the insulating layer. The first pattern generally establishes a first of a plurality of plates of a first capacitor. The via may be aligned with the second pattern. The first bump may (i) be located directly above the first plate, (ii) establish a second of the plates of the first capacitor, (iii) be suitable for flip-chip bonding and (iv) connect to the second pattern through the via such that both of the plates of the first capacitor are accessible in the intermediate conductive layer.
摘要翻译：公开了一种在芯片上制造的器件。该装置通常包括（A）在芯片的中间导电层中产生的第一图案和第二图案，（B）在中间导电层上方的绝缘层中形成的至少一个通孔，（C）产生的第一凸起在绝缘层上方的顶部导电层中。第一图案通常建立第一电容器的多个板中的第一个。通孔可以与第二图案对准。第一凸块可以（i）位于第一板的正上方，（ii）建立第一电容器的第二板，（iii）适于倒装芯片接合，以及（iv）通过通过使得第一电容器的两个板可在中间导电层中接近。

3. 发明申请

US20110006395A1 HYBRID BUMP CAPACITOR 失效
标题翻译：混合电容器
公开(公告)号：US20110006395A1
公开(公告)日：2011-01-13
申请号：US12885722
申请日：2010-09-20
申请人： Yikui (Jen) Dong , Steven L. Howard , Freeman Y. Zhong , David S. Lowrie
发明人： Yikui (Jen) Dong , Steven L. Howard , Freeman Y. Zhong , David S. Lowrie
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01G4/228 , H01G4/30 , H01L23/5223 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A device fabricated on a chip is disclosed. The device generally includes (A) a first pattern and a second pattern both created in an intermediate conductive layer of the chip, (B) at least one via created in an insulating layer above the intermediate conductive layer and (C) a first bump created in a top conductive layer above the insulating layer. The first pattern generally establishes a first of a plurality of plates of a first capacitor. The via may be aligned with the second pattern. The first bump may (i) be located directly above the first plate, (ii) establish a second of the plates of the first capacitor, (iii) be suitable for flip-chip bonding, (iv) connect to the second pattern through the via such that both of the plates of the first capacitor are accessible in the intermediate conductive layer. The first pattern and the second pattern may be shaped as interlocking combs.
摘要翻译：公开了一种在芯片上制造的器件。该装置通常包括（A）在芯片的中间导电层中产生的第一图案和第二图案，（B）在中间导电层上方的绝缘层中形成的至少一个通孔，（C）产生的第一凸起在绝缘层上方的顶部导电层中。第一图案通常建立第一电容器的多个板中的第一个。通孔可以与第二图案对准。第一凸块可以（i）位于第一板的正上方，（ii）建立第一电容器的第二板，（iii）适于倒装芯片接合，（iv）通过通过使得第一电容器的两个板可在中间导电层中接近。第一图案和第二图案可以被成形为互锁梳。

4. 发明申请

US20080018419A1 HYBRID BUMP CAPACITOR 有权
标题翻译：混合电容器
公开(公告)号：US20080018419A1
公开(公告)日：2008-01-24
申请号：US11741195
申请日：2007-04-27
申请人： Yikui Jen Dong , Steven L. Howard , Freeman Y. Zhong , David S. Lowrie
发明人： Yikui Jen Dong , Steven L. Howard , Freeman Y. Zhong , David S. Lowrie
IPC分类号： H03H7/00 , H01L21/62
CPC分类号： H01G4/228 , H01G4/30 , H01L23/5223 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A device fabricated on a chip is disclosed. The device generally includes (A) a first pattern and a second pattern both created in an intermediate conductive layer of the chip, (B) at least one via created in an insulating layer above the intermediate conductive layer and (C) a first bump created in a top conductive layer above the insulating layer. The first pattern generally establishes a first of a plurality of plates of a first capacitor. The via may be aligned with the second pattern. The first bump may (i) be located directly above the first plate, (ii) establish a second of the plates of the first capacitor, (iii) be suitable for flip-chip bonding and (iv) connect to the second pattern through the via such that both of the plates of the first capacitor are accessible in the intermediate conductive layer.
摘要翻译：公开了一种在芯片上制造的器件。器件通常包括（A）在芯片的中间导电层中产生的第一图案和第二图案，（B）在中间导电层上方的绝缘层中形成的至少一个通孔，（C）产生的第一凸起在绝缘层上方的顶部导电层中。第一图案通常建立第一电容器的多个板中的第一个。通孔可以与第二图案对准。第一凸块可以（i）位于第一板的正上方，（ii）建立第一电容器的第二板，（iii）适于倒装芯片接合，以及（iv）通过通过使得第一电容器的两个板可在中间导电层中接近。

5. 发明授权

US5001482A BiCMOS digital-to-analog converter for disk drive digital recording channel architecture 失效
标题翻译： BiCMOS数模转换器用于磁盘驱动器数字录音通道架构
公开(公告)号：US5001482A
公开(公告)日：1991-03-19
申请号：US536431
申请日：1990-06-11
申请人： Paul W. S. Chung , David S. Lowrie , Paik Saber , Chorng K. Wang
发明人： Paul W. S. Chung , David S. Lowrie , Paik Saber , Chorng K. Wang
IPC分类号： G05F3/26 , G11B20/10 , G11B20/14 , H03L7/085 , H03M1/06 , H03M1/66 , H03M1/74
CPC分类号： H03M1/0619 , G05F3/262 , G11B20/10 , G11B20/10055 , G11B20/1403 , H03L7/085 , H03M1/747
摘要： A digital-to-analog converter for use in a timing control loop. The converter includes a plurality of cells, each activated in response to a timing loop control signal. The converter also includes a resistive current mirror, with a first resistance R1, providing a reference curent which is mirrored in each cell by a current source FET. Each cell is constructed to switch the current from its current source FET through an output FET when a respective control bit provided to the cell is positive. Otherwise, the current is diverted through a sink FET. All of the cell output FETs are tied to a single resistance R2 which collects the currents of the active cells and provides the AC output of the converter. The converter's output is related only to the ratio R2/R1, thereby decoupling process, temperature, and voltage effects from the output of the converter.

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