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2. 发明授权

US07224619B2 Method and apparatus for protection from over-erasing nonvolatile memory cells 有权
标题翻译：用于防止过度擦除非易失性存储单元的方法和装置
公开(公告)号：US07224619B2
公开(公告)日：2007-05-29
申请号：US11223552
申请日：2005-09-09
申请人： Yi Ying Liao , Chih Chieh Yeh , Wen Jer Tsai , Tao-cheng Lu
发明人： Yi Ying Liao , Chih Chieh Yeh , Wen Jer Tsai , Tao-cheng Lu
IPC分类号： G11C16/04
CPC分类号： G11C16/3404
摘要： Charge trapping memory cells are protected from over-erasing in response to an erase command. For example, in response to an erase command, one bias arrangement is applied to program charge trapping memory cells, and another bias arrangement is applied to erase the charge trapping memory cells, such that the charge trapping memory cells have a higher net electron charge in the erased state than in the programmed state. In another example, an integrated circuit with an array of charge trapping memory cells has logic which responds to an erase command by applying similar bias arrangements to the charge trapping memory cells. In a further example, such an integrated circuit is manufactured.
摘要翻译：电荷捕获存储器单元被保护以响应于擦除命令而被过擦除。例如，响应于擦除命令，将一个偏置装置应用于编程电荷俘获存储器单元，并且施加另一个偏置布置以擦除电荷捕获存储器单元，使得电荷捕获存储器单元具有较高的净电子电荷擦除状态比编程状态。在另一示例中，具有电荷俘获存储器单元阵列的集成电路具有通过向电荷捕获存储器单元施加相似的偏置布置来响应擦除命令的逻辑。在另一实例中，制造这种集成电路。

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